skgehw.h

移植到2410开发板上的源代码

/*	B28_DPT_CTRL	 8 bit	Descriptor Poll Timer Ctrl Reg */
								/* Bit 7..2:	reserved */
#define DPT_START		(1<<1)	/* Bit 1:	Start Desciptor Poll Timer */
#define DPT_STOP		(1<<0)	/* Bit 0:	Stop Desciptor Poll Timer */


/*	B2_TST_CTRL1	 8 bit	Test Control Register 1 */
#define	TST_FRC_DPERR_MR	(1<<7)	/* Bit 7: force DATAPERR on MST RD */
#define	TST_FRC_DPERR_MW	(1<<6)	/* Bit 6: force DATAPERR on MST WR */
#define	TST_FRC_DPERR_TR	(1<<5)	/* Bit 5: force DATAPERR on TRG RD */
#define	TST_FRC_DPERR_TW	(1<<4)	/* Bit 4: force DATAPERR on TRG WR */
#define	TST_FRC_APERR_M		(1<<3)	/* Bit 3: force ADDRPERR on MST */
#define	TST_FRC_APERR_T		(1<<2)	/* Bit 2: force ADDRPERR on TRG */
#define	TST_CFG_WRITE_ON	(1<<1)	/* Bit 1: Enable Config Reg WR */
#define	TST_CFG_WRITE_OFF	(1<<0)	/* Bit 0: Disable Config Reg WR */

/*	B2_TST_CTRL2	 8 bit	Test Control Register 2 */
									/* Bit 7..4:	reserved */
					/* force the following error on */
					/* the next master read/write	*/
#define TST_FRC_DPERR_MR64	(1<<3)	/* Bit 3:	DataPERR RD 64	*/
#define TST_FRC_DPERR_MW64	(1<<2)	/* Bit 2:	DataPERR WR 64	*/
#define TST_FRC_APERR_1M64	(1<<1)	/* Bit 1:	AddrPERR on 1. phase */
#define TST_FRC_APERR_2M64	(1<<0)	/* Bit 0:	AddrPERR on 2. phase */

/*	B2_GP_IO	32 bit	General Purpose IO Register */
								/* Bit 31..26:	reserved */
#define	GP_DIR_9	(1L<<25)	/* Bit 25:	IO_9 direct, 0=I/1=O */
#define	GP_DIR_8	(1L<<24)	/* Bit 24:	IO_8 direct, 0=I/1=O */
#define	GP_DIR_7	(1L<<23)	/* Bit 23:	IO_7 direct, 0=I/1=O */
#define	GP_DIR_6	(1L<<22)	/* Bit 22:	IO_6 direct, 0=I/1=O */
#define	GP_DIR_5	(1L<<21)	/* Bit 21:	IO_5 direct, 0=I/1=O */
#define	GP_DIR_4	(1L<<20)	/* Bit 20:	IO_4 direct, 0=I/1=O */
#define	GP_DIR_3	(1L<<19)	/* Bit 19:	IO_3 direct, 0=I/1=O */
#define	GP_DIR_2	(1L<<18)	/* Bit 18:	IO_2 direct, 0=I/1=O */
#define	GP_DIR_1	(1L<<17)	/* Bit 17:	IO_1 direct, 0=I/1=O */
#define	GP_DIR_0	(1L<<16)	/* Bit 16:	IO_0 direct, 0=I/1=O */
								/* Bit 15..10:	reserved */
#define	GP_IO_9		(1L<<9)		/* Bit	9:	IO_9 pin */
#define	GP_IO_8		(1L<<8)		/* Bit	8:	IO_8 pin */
#define	GP_IO_7		(1L<<7)		/* Bit	7:	IO_7 pin */
#define	GP_IO_6		(1L<<6)		/* Bit	6:	IO_6 pin */
#define	GP_IO_5		(1L<<5)		/* Bit	5:	IO_5 pin */
#define	GP_IO_4		(1L<<4)		/* Bit	4:	IO_4 pin */
#define	GP_IO_3		(1L<<3)		/* Bit	3:	IO_3 pin */
#define	GP_IO_2		(1L<<2)		/* Bit	2:	IO_2 pin */
#define	GP_IO_1		(1L<<1)		/* Bit	1:	IO_1 pin */
#define	GP_IO_0		(1L<<0)		/* Bit	0:	IO_0 pin */

/*	B2_I2C_CTRL	32 bit	I2C HW Control Register */
#define	I2C_FLAG		(1UL<<31)	/* Bit 31:	Start read/write if WR*/
#define I2C_ADDR	(0x7fffL<<16)	/* Bit 30..16:	Addr to be RD/WR */
#define	I2C_DEV_SEL		(0x7fL<<9)	/* Bit 15.. 9:	I2C Device Select */
									/* Bit	8.. 5:	reserved	*/
#define I2C_BURST_LEN	(1L<<4)		/* Bit	4:	Burst Len, 1/4 bytes */
#define I2C_DEV_SIZE	(7L<<1)		/* Bit	3.. 1:	I2C Device Size	*/
#define I2C_025K_DEV	(0L<<1)		/*		0: 256 Bytes or smal. */
#define I2C_05K_DEV		(1L<<1)		/* 		1: 512	Bytes	*/
#define	I2C_1K_DEV		(2L<<1)		/*		2: 1024 Bytes	*/
#define I2C_2K_DEV		(3L<<1)		/*		3: 2048	Bytes	*/
#define	I2C_4K_DEV		(4L<<1)		/*		4: 4096 Bytes	*/
#define	I2C_8K_DEV		(5L<<1)		/*		5: 8192 Bytes	*/
#define	I2C_16K_DEV		(6L<<1)		/*		6: 16384 Bytes	*/
#define	I2C_32K_DEV		(7L<<1)		/*		7: 32768 Bytes	*/
#define I2C_STOP		(1L<<0)		/* Bit	0:	Interrupt I2C transfer*/

/*	B2_I2C_IRQ	32 bit	I2C HW IRQ Register */
								/* Bit 31..1	reserved */
#define I2C_CLR_IRQ		(1<<0)	/* Bit 0:	Clear I2C IRQ */

/*	B2_I2C_SW	32 bit	I2C HW SW Port Register */
								/* Bit 7..3:	reserved */
#define	I2C_DATA_DIR	(1<<2)	/* Bit 2:	direction of I2C_DATA */
#define I2C_DATA		(1<<1)	/* Bit 1:	I2C Data Port	*/
#define	I2C_CLK			(1<<0)	/* Bit 0:	I2C Clock Port	*/

/*
 * I2C Address
 */
#define	I2C_SENS_ADDR	LM80_ADDR	/* I2C Sensor Address, (Volt and Temp)*/


/*	B2_BSC_CTRL	 8 bit	Blink Source Counter Control */
							/* Bit 7..2:	reserved */
#define BSC_START	(1<<1)	/* Bit 1:	Start Blink Source Counter */
#define BSC_STOP	(1<<0)	/* Bit 0:	Stop Blink Source Counter */

/*	B2_BSC_STAT	 8 bit	Blink Source Counter Status */
							/* Bit 7..1:	reserved */
#define BSC_SRC		(1<<0)	/* Bit 0:	Blink Source, 0=Off / 1=On */

/*	B2_BSC_TST	16 bit	Blink Source Counter Test Reg */
#define	BSC_T_ON	(1<<2)	/* Bit 2:	Test mode on */
#define	BSC_T_OFF	(1<<1)	/* Bit 1:	Test mode off */
#define	BSC_T_STEP	(1<<0)	/* Bit 0:	Test step */


/*	B3_RAM_ADDR	32 bit	RAM Address, to read or write */
					/* Bit 31..19:	reserved */
#define RAM_ADR_RAN	0x0007ffffL	/* Bit 18.. 0:	RAM Address Range */

/* RAM Interface Registers */
/*	B3_RI_CTRL	16 bit	RAM Iface Control Register */
								/* Bit 15..10:	reserved */
#define RI_CLR_RD_PERR	(1<<9)	/* Bit	9:	Clear IRQ RAM Read Parity Err */
#define RI_CLR_WR_PERR	(1<<8)	/* Bit	8:	Clear IRQ RAM Write Parity Err*/
								/* Bit	7..2:	reserved */
#define RI_RST_CLR		(1<<1)	/* Bit	1:	Clear RAM Interface Reset */
#define RI_RST_SET		(1<<0)	/* Bit	0:	Set RAM Interface Reset */

/*	B3_RI_TEST	 8 bit	RAM Iface Test Register */
								/* Bit 15..4:	reserved */
#define RI_T_EV			(1<<3)	/* Bit	3:	Timeout Event occured */
#define RI_T_ON			(1<<2)	/* Bit	2:	Timeout Timer Test On */
#define RI_T_OFF		(1<<1)	/* Bit	1:	Timeout Timer Test Off */
#define RI_T_STEP		(1<<0)	/* Bit	0:	Timeout Timer Step */

/* MAC Arbiter Registers */
/*	B3_MA_TO_CTRL	16 bit	MAC Arbiter Timeout Ctrl Reg */
								/* Bit 15..4:	reserved */
#define MA_FOE_ON		(1<<3)	/* Bit	3:	XMAC Fast Output Enable ON */
#define MA_FOE_OFF		(1<<2)	/* Bit	2:	XMAC Fast Output Enable OFF */
#define MA_RST_CLR		(1<<1)	/* Bit	1:	Clear MAC Arbiter Reset */
#define MA_RST_SET		(1<<0)	/* Bit	0:	Set MAC Arbiter Reset */

/*	B3_MA_RC_CTRL	16 bit	MAC Arbiter Recovery Ctrl Reg */
								/* Bit 15..8:	reserved */
#define MA_ENA_REC_TX2	(1<<7)	/* Bit	7:	Enable Recovery Timer TX2 */
#define MA_DIS_REC_TX2	(1<<6)	/* Bit	6:	Disable Recovery Timer TX2 */
#define MA_ENA_REC_TX1	(1<<5)	/* Bit	5:	Enable Recovery Timer TX1 */
#define MA_DIS_REC_TX1	(1<<4)	/* Bit	4:	Disable Recovery Timer TX1 */
#define MA_ENA_REC_RX2	(1<<3)	/* Bit	3:	Enable Recovery Timer RX2 */
#define MA_DIS_REC_RX2	(1<<2)	/* Bit	2:	Disable Recovery Timer RX2 */
#define MA_ENA_REC_RX1	(1<<1)	/* Bit	1:	Enable Recovery Timer RX1 */
#define MA_DIS_REC_RX1	(1<<0)	/* Bit	0:	Disable Recovery Timer RX1 */

/* Packet Arbiter Registers */
/*	B3_PA_CTRL	16 bit	Packet Arbiter Ctrl Register */
								/* Bit 15..14:	reserved */
#define PA_CLR_TO_TX2	(1<<13)	/* Bit 13:	Clear IRQ Packet Timeout TX2 */
#define PA_CLR_TO_TX1	(1<<12)	/* Bit 12:	Clear IRQ Packet Timeout TX1 */
#define PA_CLR_TO_RX2	(1<<11)	/* Bit 11:	Clear IRQ Packet Timeout RX2 */
#define PA_CLR_TO_RX1	(1<<10)	/* Bit 10:	Clear IRQ Packet Timeout RX1 */
#define PA_ENA_TO_TX2	(1<<9)	/* Bit	9:	Enable Timeout Timer TX2 */
#define PA_DIS_TO_TX2	(1<<8)	/* Bit	8:	Disable Timeout Timer TX2 */
#define PA_ENA_TO_TX1	(1<<7)	/* Bit	7:	Enable Timeout Timer TX1 */
#define PA_DIS_TO_TX1	(1<<6)	/* Bit	6:	Disable Timeout Timer TX1 */
#define PA_ENA_TO_RX2	(1<<5)	/* Bit	5:	Enable Timeout Timer RX2 */
#define PA_DIS_TO_RX2	(1<<4)	/* Bit	4:	Disable Timeout Timer RX2 */
#define PA_ENA_TO_RX1	(1<<3)	/* Bit	3:	Enable Timeout Timer RX1 */
#define PA_DIS_TO_RX1	(1<<2)	/* Bit	2:	Disable Timeout Timer RX1 */
#define PA_RST_CLR		(1<<1)	/* Bit	1:	Clear MAC Arbiter Reset */
#define PA_RST_SET		(1<<0)	/* Bit	0:	Set MAC Arbiter Reset */

#define PA_ENA_TO_ALL	(PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
						PA_ENA_TO_TX1 | PA_ENA_TO_TX2)

/* Rx/Tx Path related Arbiter Test Registers */
/*	B3_MA_TO_TEST	16 bit	MAC Arbiter Timeout Test Reg */
/*	B3_MA_RC_TEST	16 bit	MAC Arbiter Recovery Test Reg */
/*	B3_PA_TEST	16 bit	Packet Arbiter Test Register */
/*			Bit 15, 11, 7, and 3 are reserved in B3_PA_TEST */
#define TX2_T_EV	(1<<15)	/* Bit 15: 	TX2 Timeout/Recv Event occured*/
#define TX2_T_ON	(1<<14)	/* Bit 14:	TX2 Timeout/Recv Timer Test On*/
#define TX2_T_OFF	(1<<13)	/* Bit 13:	TX2 Timeout/Recv Timer Tst Off*/
#define TX2_T_STEP	(1<<12)	/* Bit 12:	TX2 Timeout/Recv Timer Step */
#define TX1_T_EV	(1<<11)	/* Bit 11:	TX1 Timeout/Recv Event occured*/
#define TX1_T_ON	(1<<10)	/* Bit 10:	TX1 Timeout/Recv Timer Test On*/
#define TX1_T_OFF	(1<<9)	/* Bit	9:	TX1 Timeout/Recv Timer Tst Off*/
#define TX1_T_STEP	(1<<8)	/* Bit	8:	TX1 Timeout/Recv Timer Step */
#define RX2_T_EV	(1<<7)	/* Bit	7:	RX2 Timeout/Recv Event occured*/
#define RX2_T_ON	(1<<6)	/* Bit	6:	RX2 Timeout/Recv Timer Test On*/
#define RX2_T_OFF	(1<<5)	/* Bit	5:	RX2 Timeout/Recv Timer Tst Off*/
#define RX2_T_STEP	(1<<4)	/* Bit	4:	RX2 Timeout/Recv Timer Step */
#define RX1_T_EV	(1<<3)	/* Bit	3:	RX1 Timeout/Recv Event occured*/
#define RX1_T_ON	(1<<2)	/* Bit	2:	RX1 Timeout/Recv Timer Test On*/
#define RX1_T_OFF	(1<<1)	/* Bit	1:	RX1 Timeout/Recv Timer Tst Off*/
#define RX1_T_STEP	(1<<0)	/* Bit	0:	RX1 Timeout/Recv Timer Step */


/* Transmit Arbiter Registers MAC 1 and 2, user MR_ADDR() to address */
/*	TXA_ITI_INI	32 bit	Tx Arb Interval Timer Init Val */
/*	TXA_ITI_VAL	32 bit	Tx Arb Interval Timer Value */
/*	TXA_LIM_INI	32 bit	Tx Arb Limit Counter Init Val */
/*	TXA_LIM_VAL	32 bit	Tx Arb Limit Counter Value */
								/* Bit 31..24:	reserved */
#define	TXA_MAX_VAL	0x00ffffffL	/* Bit 23.. 0:	Max TXA Timer/Cnt Val */

/*	TXA_CTRL	 8 bit	Tx Arbiter Control Register */
#define TXA_ENA_FSYNC	(1<<7)	/* Bit 7:	Enable force of sync tx queue */
#define TXA_DIS_FSYNC	(1<<6)	/* Bit 6:	Disable force of sync tx queue*/
#define TXA_ENA_ALLOC	(1<<5)	/* Bit 5:	Enable alloc of free bandwidth*/
#define TXA_DIS_ALLOC	(1<<4)	/* Bit 4:	Disabl alloc of free bandwidth*/
#define TXA_START_RC	(1<<3)	/* Bit 3:	Start sync Rate Control */
#define TXA_STOP_RC		(1<<2)	/* Bit 2:	Stop sync Rate Control */
#define TXA_ENA_ARB		(1<<1)	/* Bit 1:	Enable Tx Arbiter */
#define TXA_DIS_ARB		(1<<0)	/* Bit 0:	Disable Tx Arbiter */

/*	TXA_TEST	 8 bit	Tx Arbiter Test Register */
				/* Bit 7..6:	reserved */
#define TXA_INT_T_ON	(1<<5)	/* Bit 5:	Tx Arb Interval Timer Test On */
#define TXA_INT_T_OFF	(1<<4)	/* Bit 4:	Tx Arb Interval Timer Test Off*/
#define TXA_INT_T_STEP	(1<<3)	/* Bit 3:	Tx Arb Interval Timer Step */
#define TXA_LIM_T_ON	(1<<2)	/* Bit 2:	Tx Arb Limit Timer Test On */
#define TXA_LIM_T_OFF	(1<<1)	/* Bit 1:	Tx Arb Limit Timer Test Off */
#define TXA_LIM_T_STEP	(1<<0)	/* Bit 0:	Tx Arb Limit Timer Step */

/*	TXA_STAT	 8 bit	Tx Arbiter Status Register */
								/* Bit 7..1:	reserved */
#define	TXA_PRIO_XS		(1<<0)	/* Bit 0:	sync queue has prio to send */

/*	Q_BC	32 bit	Current Byte Counter */
				/* Bit 31..16:	reserved */
#define BC_MAX			0xffff	/* Bit 15.. 0:	Byte counter */

/* BMU Control Status Registers */
/*	B0_R1_CSR	32 bit	BMU Ctrl/Stat Rx Queue 1 */
/*	B0_R2_CSR	32 bit	BMU Ctrl/Stat Rx Queue 2 */
/*	B0_XA1_CSR	32 bit	BMU Ctrl/Stat Sync Tx Queue 1 */
/*	B0_XS1_CSR	32 bit	BMU Ctrl/Stat Async Tx Queue 1 */
/*	B0_XA2_CSR	32 bit	BMU Ctrl/Stat Sync Tx Queue 2 */
/*	B0_XS2_CSR	32 bit	BMU Ctrl/Stat Async Tx Queue 2 */
/*	Q_CSR	32 bit	BMU Control/Status Register */
									/* Bit 31..25:	reserved */
#define CSR_SV_IDLE		(1L<<24)	/* Bit 24: 	BMU SM Idle */
									/* Bit 23..22:	reserved */
#define	CSR_DESC_CLR	(1L<<21)	/* Bit 21:	Clear Reset for Descr */
#define	CSR_DESC_SET	(1L<<20)	/* Bit 20:	Set Reset for Descr */
#define	CSR_FIFO_CLR	(1L<<19)	/* Bit 19:	Clear Reset for FIFO */
#define	CSR_FIFO_SET	(1L<<18)	/* Bit 18:	Set Reset for FIFO */
#define	CSR_HPI_RUN		(1L<<17)	/* Bit 17:	Release HPI SM */
#define	CSR_HPI_RST		(1L<<16)	/* Bit 16:	Reset HPI SM to Idle */
#define	CSR_SV_RUN		(1L<<15)	/* Bit 15:	Release Supervisor SM */
#define	CSR_SV_RST		(1L<<14)	/* Bit 14:	Reset Supervisor SM */
#define	CSR_DREAD_RUN	(1L<<13)	/* Bit 13:	Release Descr Read SM */
#define	CSR_DREAD_RST	(1L<<12)	/* Bit 12:	Reset Descr Read SM */
#define	CSR_DWRITE_RUN	(1L<<11)	/* Bit 11:	Rel. Descr Write SM */
#define	CSR_DWRITE_RST	(1L<<10)	/* Bit 10:	Reset Descr Write SM */
#define	CSR_TRANS_RUN	(1L<<9)		/* Bit	9:	Release Transfer SM */
#define	CSR_TRANS_RST	(1L<<8)		/* Bit	8:	Reset Transfer SM */
#define CSR_ENA_POL		(1L<<7)		/* Bit	7:	Enable Descr Polling */
#define CSR_DIS_POL		(1L<<6)		/* Bit	6:	Disable Descr Polling */
#define CSR_STOP		(1L<<5)		/* Bit	5:	Stop Rx/Tx Queue */
#define	CSR_START		(1L<<4)		/* Bit	4:	Start Rx/Tx Queue */
#define	CSR_IRQ_CL_P	(1L<<3)		/* Bit	3: (Rx)	Clear Parity IRQ */
#define	CSR_IRQ_CL_B	(1L<<2)		/* Bit	2:	Clear EOB IRQ */
#define	CSR_IRQ_CL_F	(1L<<1)		/* Bit	1:	Clear EOF IRQ */
#define	CSR_IRQ_CL_C	(1L<<0)		/* Bit	0:	Clear ERR IRQ */

#define CSR_SET_RESET	(CSR_DESC_SET|CSR_FIFO_SET|CSR_HPI_RST|CSR_SV_RST|\
						CSR_DREAD_RST|CSR_DWRITE_RST|CSR_TRANS_RST)
#define CSR_CLR_RESET	(CSR_DESC_CLR|CSR_FIFO_CLR|CSR_HPI_RUN|CSR_SV_RUN|\
						CSR_DREAD_RUN|CSR_DWRITE_RUN|CSR_TRANS_RUN)


/*	Q_F	32 bit	Flag Register */
					/* Bit 28..31:	reserved */
#define F_ALM_FULL		(1L<<27) (Rx)	/* Bit 27: (Rx)	FIFO almost full */
#define F_EMPTY			(1L<<27) (Tx)	/* Bit 27: (Tx)	FIFO empty flag */
#define F_FIFO_EOF		(1L<<26)	/* Bit 26: 	Fag bit in FIFO */
#define F_WM_REACHED	(1L<<25)	/* Bit 25: 	Watermark reached */
									/* Bit 24:	reserved */
#define F_FIFO_LEVEL	(0x1fL<<16)	/* Bit 23..16:	# of Qwords in FIFO */
									/* Bit 15..11: 	reserved */
#define F_WATER_MARK	0x0007ffL	/* Bit 10.. 0:	Watermark */

/*	Q_T1	32 bit	Test Register 1 */
/*		Holds four State Machine control Bytes */
#define	SM_CRTL_SV	(0xffL<<24)	/* Bit 31..24:	Control Supervisor SM */
#define	SM_CRTL_RD	(0xffL<<16)	/* Bit 23..16:	Control Read Desc SM */
#define	SM_CRTL_WR	(0xffL<<8)	/* Bit 15.. 8:	Control Write Desc SM */
#define	SM_CRTL_TR	(0xffL<<0)	/* Bit	7.. 0:	Control Transfer SM */

/*	Q_T1_TR	 8 bit	Test Register 1 Transfer SM */
/*	Q_T1_WR	 8 bit	Test Register 1 Write Descriptor SM */
/*	Q_T1_RD	 8 bit	Test Register 1 Read Descriptor SM */
/*	Q_T1_SV	 8 bit	Test Register 1 Supervisor SM */
/* The control status byte of each machine looks like ... */
#define	SM_STATE	0xf0	/* Bit 7..4:	State which shall be loaded */
#define	SM_LOAD		(1<<3)	/* Bit 3:	Load the SM with SM_STATE */
#define	SM_TEST_ON	(1<<2)	/* Bit 2:	Switch on SM Test Mode */
#define	SM_TEST_OFF	(1<<1)	/* Bit 1:	Go off the Test Mode */
#define	SM_STEP		(1<<0)	/* Bit 0:	Step the State Machine */
/* The encoding of the states is not supported by the Diagnostics Tool */

/*	Q_T2	32 bit	Test Register 2	*/
				/* Bit 31..8:	reserved */
#define	T2_AC_T_ON	(1<<7)	/* Bit 7:	Address Counter Test Mode on */
#define	T2_AC_T_OFF	(1<<6)	/* Bit 6:	Address Counter Test Mode off*/
#define	T2_BC_T_ON	(1<<5)	/* Bit 5:	Byte Counter Test Mode on */
#define	T2_BC_T_OFF	(1<<4)	/* Bit 4:	Byte Counter Test Mode off */
#define	T2_STEP04	(1<<3)	/* Bit 3:	Inc AC/Dec BC by 4 */