skgehw.h

移植到2410开发板上的源代码

 */
/* External registers */
#define B6_EXT_REG		0x0300

/*
 *	Bank 7
 */
/* This is a copy of the Configuration register file (lower half) */
#define B7_CFG_SPC		0x0380

/*
 *	Bank 8 - 15
 */
/* Receive and Transmit Queue Registers, use Q_ADDR() to access */
#define	B8_Q_REGS		0x0400

/* Queue Register Offsets, use Q_ADDR() to access */
#define Q_D		0x00	/* 8*32	bit	Current Descriptor */
#define Q_DA_L	0x20	/* 32 bit	Current Descriptor Address Low dWord */
#define Q_DA_H	0x24	/* 32 bit	Current Descriptor Address High dWord */
#define Q_AC_L	0x28	/* 32 bit	Current Address Counter Low dWord */
#define Q_AC_H	0x2c	/* 32 bit	Current Address Counter High dWord */
#define Q_BC	0x30	/* 32 bit	Current Byte Counter */
#define Q_CSR	0x34	/* 32 bit	BMU Control/Status Register */
#define Q_F		0x38	/* 32 bit	Flag Register */
#define Q_T1	0x3c	/* 32 bit	Test Register 1 */
#define Q_T1_TR	0x3c	/*  8 bit	Test Register 1 Transfer SM */
#define Q_T1_WR	0x3d	/*  8 bit	Test Register 1 Write Descriptor SM */
#define Q_T1_RD	0x3e	/*  8 bit	Test Register 1 Read Descriptor SM */
#define Q_T1_SV	0x3f	/*  8 bit	Test Register 1 Supervisor SM */
#define Q_T2	0x40	/* 32 bit	Test Register 2	*/
#define Q_T3	0x44	/* 32 bit	Test Register 3	*/
	/* 0x48 - 0x7f:	reserved */

/*
 *	Bank 16 - 23
 */
/* RAM Buffer Registers */
#define	B16_RAM_REGS	0x0800

/* RAM Buffer Register Offsets */
/* use RB_ADDR(Queue,Offs) to address */
#define RB_START	0x00	/* 32 bit	RAM Buffer Start Address */
#define RB_END		0x04	/* 32 bit	RAM Buffer End Address */
#define RB_WP		0x08	/* 32 bit	RAM Buffer Write Pointer */
#define RB_RP		0x0c	/* 32 bit	RAM Buffer Read Pointer */
#define RB_RX_UTPP	0x10	/* 32 bit	Rx Upper Threshold, Pause Pack*/
#define RB_RX_LTPP	0x14	/* 32 bit	Rx Lower Threshold, Pause Pack*/
#define RB_RX_UTHP	0x18	/* 32 bit	Rx Upper Threshold, High Prio */
#define RB_RX_LTHP	0x1c	/* 32 bit	Rx Lower Threshold, High Prio */
	/* 0x10 - 0x1f:		reserved for Tx RAM Buffer Registers */
#define RB_PC		0x20	/* 32 bit	RAM Buffer Packet Counter */
#define RB_LEV		0x24	/* 32 bit	RAM Buffer Level Register */
#define RB_CTRL		0x28	/*  8 bit	RAM Buffer Control Register */
#define RB_TST1		0x29	/*  8 bit	RAM Buffer Test Register 1 */
#define RB_TST2		0x2A	/*  8 bit	RAM Buffer Test Register 2 */
	/* 0x2c - 0x7f:		reserved */

/*
 *	Bank 24 - 25
 */
/* Receive MAC FIFO, Receive LED, and Link Sync regs, use MR_ADDR() to address*/
#define RX_MFF_EA		0x0c00	/* 32 bit	Receive MAC FIFO End Address */
#define RX_MFF_WP		0x0c04	/* 32 bit 	Receive MAC FIFO Write Pointer*/
	/* 0x0c08 - 0x0c0b	reserved */
#define RX_MFF_RP		0x0c0c	/* 32 bit	Receive MAC FIFO Read Pointer */
#define RX_MFF_PC		0x0c10	/* 32 bit	Receive MAC FIFO Packet Cnt */
#define RX_MFF_LEV		0x0c14	/* 32 bit	Receive MAC FIFO Level */
#define RX_MFF_CTRL1	0x0c18	/* 16 bit	Receive MAC FIFO Control Reg 1*/
#define RX_MFF_STAT_TO	0x0c1a	/*  8 bit	Receive MAC Status Timeout */
#define RX_MFF_TIST_TO	0x0c1b	/*  8 bit	Receive MAC Timestamp Timeout */
#define RX_MFF_CTRL2	0x0c1c	/*  8 bit	Receive MAC FIFO Control Reg 2*/
#define RX_MFF_TST1		0x0c1d	/*  8 bit	Receive MAC FIFO Test Reg 1 */
#define RX_MFF_TST2		0x0c1e	/*  8 bit	Receive MAC FIFO Test Reg 2 */
	/* 0x0c1f		reserved */
#define RX_LED_INI		0x0c20	/* 32 bit	Receive LED Cnt Init Value */
#define RX_LED_VAL		0x0c24	/* 32 bit	Receive LED Cnt Current Value */
#define RX_LED_CTRL		0x0c28	/*  8 bit	Receive LED Cnt Control Reg */
#define RX_LED_TST		0x0c29	/*  8 bit	Receive LED Cnt Test Register */
	/* 0x0c2a - 0x0c2f	reserved */
#define LNK_SYNC_INI	0x0c30	/* 32 bit	Link Sync Cnt Init Value */
#define LNK_SYNC_VAL	0x0c34	/* 32 bit	Link Sync Cnt Current Value */
#define LNK_SYNC_CTRL	0x0c38	/*  8 bit	Link Sync Cnt Control Register*/
#define LNK_SYNC_TST	0x0c39	/*  8 bit	Link Sync Cnt Test Register */
	/* 0x0c3a - 0x0c3b	reserved */
#define LNK_LED_REG		0x0c3c	/*  8 bit	Link LED Register */
	/* 0x0c3d - 0x0c7f	reserved */

/*
 *	Bank 26 - 27
 */
/* Transmit MAC FIFO and Transmit LED Registers, use MR_ADDR() to address */
#define TX_MFF_EA		0x0d00	/* 32 bit	Transmit MAC FIFO End Address */
#define TX_MFF_WP		0x0d04	/* 32 bit 	Transmit MAC FIFO WR Pointer */
#define TX_MFF_WSP		0x0d08	/* 32 bit	Transmit MAC FIFO WR Shadow Pt*/
#define TX_MFF_RP		0x0d0c	/* 32 bit	Transmit MAC FIFO RD Pointer */
#define TX_MFF_PC		0x0d10	/* 32 bit	Transmit MAC FIFO Packet Cnt */
#define TX_MFF_LEV		0x0d14	/* 32 bit	Transmit MAC FIFO Level */
#define TX_MFF_CTRL1	0x0d18	/* 16 bit	Transmit MAC FIFO Ctrl Reg 1 */
#define TX_MFF_WAF		0x0d1a	/*  8 bit	Transmit MAC Wait after flush*/
	/* 0x0c1b		reserved */
#define TX_MFF_CTRL2	0x0d1c	/*  8 bit	Transmit MAC FIFO Ctrl Reg 2 */
#define TX_MFF_TST1		0x0d1d	/*  8 bit	Transmit MAC FIFO Test Reg 1 */
#define TX_MFF_TST2		0x0d1e	/*  8 bit	Transmit MAC FIFO Test Reg 2 */
	/* 0x0d1f		reserved */
#define TX_LED_INI		0x0d20	/* 32 bit	Transmit LED Cnt Init Value */
#define TX_LED_VAL		0x0d24	/* 32 bit	Transmit LED Cnt Current Val */
#define TX_LED_CTRL		0x0d28	/*  8 bit	Transmit LED Cnt Control Reg */
#define TX_LED_TST		0x0d29	/*  8 bit	Transmit LED Cnt Test Register*/
	/* 0x0d2a - 0x0d7f	reserved */

/*
 *	Bank 28
 */
/* Descriptor Poll Timer Registers */
#define B28_DPT_INI		0x0e00	/* 32 bit	Descriptor Poll Timer Init Val*/
#define B28_DPT_VAL		0x0e04	/* 32 bit	Descriptor Poll Timer Curr Val*/
#define B28_DPT_CTRL	0x0e08	/*  8 bit	Descriptor Poll Timer Ctrl Reg*/
	/* 0x0e09:		reserved */
#define B28_DPT_TST		0x0e0a	/*  8 bit	Descriptor Poll Timer Test Reg*/
	/* 0x0e0b - 0x0e8f:	reserved */

/*
 *	Bank 29 - 31
 */
/* 0x0e90 - 0x0fff:	reserved */

/*
 *	Bank 0x20 - 0x3f
 */
/* 0x1000 - 0x1fff:	reserved */

/*
 *	Bank 0x40 - 0x4f
 */
/* XMAC 1 registers */
#define B40_XMAC1	0x2000

/*
 *	Bank 0x50 - 0x5f
 */
/* 0x2800 - 0x2fff:	reserved */

/*
 *	Bank 0x60 - 0x6f
 */
/* XMAC 2 registers */
#define B40_XMAC2	0x3000

/*
 *	Bank 0x70 - 0x7f
 */
/* 0x3800 - 0x3fff:	reserved */

/*
 *	Control Register Bit Definitions:
 */
/*	B0_RAP		8 bit	Register Address Port */
				/* Bit 7:	reserved */
#define	RAP_RAP			0x3f	/* Bit 6..0:	0 = block 0, .., 6f = block 6f*/

/*	B0_CTST		16 bit	Control/Status register */
				/* Bit 15..10:	reserved */
#define CS_BUS_CLOCK	(1<<9)	/* Bit	9:	Bus Clock 0/1 = 33/66MHz */
#define CS_BUS_SLOT_SZ	(1<<8)	/* Bit	8:	Slot Size 0/1 = 32/64 bit slot*/
#define CS_ST_SW_IRQ	(1<<7)	/* Bit	7:	Set IRQ SW Request	*/
#define CS_CL_SW_IRQ	(1<<6)	/* Bit	6:	Clear IRQ SW Request	*/
#define CS_STOP_DONE	(1<<5)	/* Bit	5:	Stop Master is finished */
#define	CS_STOP_MAST	(1<<4)	/* Bit	4:	Command Bit to stop the master*/
#define	CS_MRST_CLR		(1<<3)	/* Bit	3:	Clear Master reset	*/
#define	CS_MRST_SET		(1<<2)	/* Bit	2:	Set Master reset	*/
#define	CS_RST_CLR		(1<<1)	/* Bit	1:	Clear Software reset	*/
#define	CS_RST_SET		(1<<0)	/* Bit	0:	Set Software reset	*/

/*	B0_LED		 8 Bit	LED register */
				/* Bit 7..2:	reserved */
#define LED_STAT_ON		(1<<1)	/* Bit 1:	Status LED on	*/
#define LED_STAT_OFF	(1<<0)	/* Bit 0:	Status LED off	*/

/*	B0_ISRC		32 bit	Interrupt Source Register */
/*	B0_IMSK		32 bit	Interrupt Mask Register */
/*	B0_SP_ISRC	32 bit	Special Interrupt Source Reg */
/*	B2_IRQM_MSK 	32 bit	IRQ Moderation Mask */
#define IS_ALL_MSK		0xbfffffffL	/* 		All Interrupt bits */
#define IS_HW_ERR		(1UL<<31)	/* Bit 31:	Interrupt HW Error */
									/* Bit 30:	reserved */
#define IS_PA_TO_RX1	(1L<<29)	/* Bit 29:	Packet Arb Timeout Rx1*/
#define IS_PA_TO_RX2	(1L<<28)	/* Bit 28:	Packet Arb Timeout Rx2*/
#define IS_PA_TO_TX1	(1L<<27)	/* Bit 27:	Packet Arb Timeout Tx1*/
#define IS_PA_TO_TX2	(1L<<26)	/* Bit 26:	Packet Arb Timeout Tx2*/
#define IS_I2C_READY	(1L<<25)	/* Bit 25:	IRQ on end of I2C tx */
#define IS_IRQ_SW		(1L<<24)	/* Bit 24:	SW forced IRQ	*/
#define IS_EXT_REG		(1L<<23)	/* Bit 23:	IRQ from external reg */
#define	IS_TIMINT		(1L<<22)	/* Bit 22:	IRQ from Timer	*/
#define IS_MAC1			(1L<<21)	/* Bit 21:	IRQ from MAC 1	*/
#define IS_LNK_SYNC_M1	(1L<<20)	/* Bit 20:	Link Sync Cnt wrap M1 */
#define IS_MAC2			(1L<<19)	/* Bit 19:	IRQ from MAC 2	*/
#define IS_LNK_SYNC_M2	(1L<<18)	/* Bit 18:	Link Sync Cnt wrap M2 */
/* Receive Queue 1 */
#define	IS_R1_B			(1L<<17)	/* Bit 17:	Q_R1 End of Buffer */
#define	IS_R1_F			(1L<<16)	/* Bit 16:	Q_R1 End of Frame */
#define	IS_R1_C			(1L<<15)	/* Bit 15:	Q_R1 Encoding Error */
/* Receive Queue 2 */
#define	IS_R2_B			(1L<<14)	/* Bit 14:	Q_R2 End of Buffer */
#define	IS_R2_F			(1L<<13)	/* Bit 13:	Q_R2 End of Frame */
#define	IS_R2_C			(1L<<12)	/* Bit 12:	Q_R2 Encoding Error */
/* Synchronous Transmit Queue 1 */
#define	IS_XS1_B		(1L<<11)	/* Bit 11:	Q_XS1 End of Buffer */
#define	IS_XS1_F		(1L<<10)	/* Bit 10:	Q_XS1 End of Frame */
#define	IS_XS1_C		(1L<<9)		/* Bit	9:	Q_XS1 Encoding Error */
/* Asynchronous Transmit Queue 1 */
#define	IS_XA1_B		(1L<<8)		/* Bit	8:	Q_XA1 End of Buffer */
#define	IS_XA1_F		(1L<<7)		/* Bit	7:	Q_XA1 End of Frame */
#define	IS_XA1_C		(1L<<6)		/* Bit	6:	Q_XA1 Encoding Error */
/* Synchronous Transmit Queue 2 */
#define	IS_XS2_B		(1L<<5)		/* Bit	5:	Q_XS2 End of Buffer */
#define	IS_XS2_F		(1L<<4)		/* Bit	4:	Q_XS2 End of Frame */
#define	IS_XS2_C		(1L<<3)		/* Bit	3:	Q_XS2 Encoding Error */
/* Asynchronous Transmit Queue 2 */
#define	IS_XA2_B		(1L<<2)		/* Bit	2:	Q_XA2 End of Buffer */
#define	IS_XA2_F		(1L<<1)		/* Bit	1:	Q_XA2 End of Frame */
#define	IS_XA2_C		(1L<<0)		/* Bit	0:	Q_XA2 Encoding Error */


/*	B0_HWE_ISRC	32 bit	HW Error Interrupt Src Reg */
/*	B0_HWE_IMSK	32 bit	HW Error Interrupt Mask Reg */
/*	B2_IRQM_HWE_MSK 32 bit	IRQ Moderation HW Error Mask */
#define IS_ERR_MSK		0x00000fffL	/* 		All Error bits */
									/* Bit 31..12:	reserved */
#define	IS_IRQ_MST_ERR	(1L<<11)	/* Bit 11:	IRQ master error */
									/*	PERR,RMABORT,RTABORT,DATAPERR */
#define	IS_IRQ_STAT		(1L<<10)	/* Bit 10:	IRQ status execption */
									/*	RMABORT, RTABORT, DATAPERR */
#define IS_NO_STAT_M1	(1L<<9)		/* Bit	9:	No Rx Status from MAC1*/
#define IS_NO_STAT_M2	(1L<<8)		/* Bit	8:	No Rx Status from MAC2*/
#define IS_NO_TIST_M1	(1L<<7)		/* Bit	7:	No Timestamp from MAC1*/
#define IS_NO_TIST_M2	(1L<<6)		/* Bit	6:	No Timestamp from MAC2*/
#define IS_RAM_RD_PAR	(1L<<5)		/* Bit	5:	RAM Read Parity Error */
#define IS_RAM_WR_PAR	(1L<<4)		/* Bit	4:	RAM Write Parity Error*/
#define IS_M1_PAR_ERR	(1L<<3)		/* Bit	3:	MAC 1 Parity Error */
#define IS_M2_PAR_ERR	(1L<<2)		/* Bit	2:	MAC 2 Parity Error */
#define IS_R1_PAR_ERR	(1L<<1)		/* Bit	1:	Queue R1 Parity Error */
#define IS_R2_PAR_ERR	(1L<<0)		/* Bit	0:	Queue R2 Parity Error */

/*	B2_CONN_TYP	 8 bit	Connector type */
/*	B2_PMD_TYP	 8 bit	PMD type */
/*	Values of connector and PMD type comply to SysKonnect internal std */

/*	B2_MAC_CFG	 8 bit	MAC Configuration */
								/* Bit 7..2:	reserved */
#define	CFG_DIS_M2_CLK	(1<<1)	/* Bit 1:	Disable Clock for 2nd MAC */
#define CFG_SNG_MAC		(1<<0)	/* Bit 0:	MAC Config: 1=2 MACs / 0=1 MAC*/

/*	B2_CHIP_REV	 8 bit 	Queen Chip Revision Number */
#define FIRST_CHIP_REV	0x0a	/* Initial Revision Value */

/*	B2_FAR		32 bit	Flash-Prom Addr Reg/Cnt */
#define	FAR_ADDR		0x1ffffL	/* Bit 16..0:	FPROM Address mask */

/*	B2_LD_CRTL	 8 bit	EPROM loader control register */
/*	Bits are currently reserved */

/*	B2_LD_TEST	 8 bit	EPROM loader test register */
								/* Bit 7..4:	reserved */
#define	LD_T_ON			(1<<3)	/* Bit 3:	Loader Testmode on */
#define	LD_T_OFF		(1<<2)	/* Bit 2:	Loader Testmode off */
#define	LD_T_STEP		(1<<1)	/* Bit 1:	Decrement FPROM addr. Counter */
#define	LD_START		(1<<0)	/* Bit 0:	Start loading FPROM */

/*
 *	Timer Section
 */
/*	B2_TI_CRTL	 8 bit	Timer control */
/*	B2_IRQM_CTRL	 8 bit	IRQ Moderation Timer Control */
								/* Bit 7..3:	reserved */
#define TIM_START		(1<<2)	/* Bit 2:	Start Timer */
#define TIM_STOP		(1<<1)	/* Bit 1:	Stop Timer */
#define TIM_CLR_IRQ		(1<<0)	/* Bit 0:	Clear Timer IRQ, (!IRQM) */

/*	B2_TI_TEST	 8 Bit	Timer Test */
/*	B2_IRQM_TEST	 8 bit	IRQ Moderation Timer Test */
/*	B28_DPT_TST	 8 bit	Descriptor Poll Timer Test Reg */
								/* Bit 7..3:	reserved */
#define	TIM_T_ON		(1<<2)	/* Bit 2:	Test mode on */
#define	TIM_T_OFF		(1<<1)	/* Bit 1:	Test mode off */
#define	TIM_T_STEP		(1<<0)	/* Bit 0:	Test step */

/*	B28_DPT_INI	32 bit	Descriptor Poll Timer Init Val */
/*	B28_DPT_VAL	32 bit	Descriptor Poll Timer Curr Val */
								/* Bit 31..24:	reserved */
#define DPT_MSK		0x00ffffffL	/* Bit 23.. 0:	Desc Poll Timer Bits */