skgehw.h

移植到2410开发板上的源代码

#define	PCI_MEM64BIT	(2L<<1)		/* Base addr anywhere in 64 Bit range */
#define	PCI_MEMSPACE	(1L<<0)		/* Bit	0:	Memory Space Indic. */

/*	PCI_BASE_2ND	32 bit	2nd Base address */
#define	PCI_IOBASE		0xffffff00L	/* Bit 31..8:	I/O Base address */
#define	PCI_IOSIZE		0x000000fcL	/* Bit	7..2:	I/O Size Requirements */
									/* Bit	1:	reserved */
#define	PCI_IOSPACE		(1L<<0)		/* Bit	0:	I/O Space Indicator */

/*	PCI_BASE_ROM	32 bit	Expansion ROM Base Address */
#define	PCI_ROMBASE		(0xfffeL<<17)	/* Bit 31..17:	ROM BASE address (1st)*/
#define	PCI_ROMBASZ		(0x1cL<<14)	/* Bit 16..14:	Treat as BASE or SIZE */
#define	PCI_ROMSIZE		(0x38L<<11)	/* Bit 13..11:	ROM Size Requirements */
									/* Bit 10.. 1:	reserved */
#define	PCI_ROMEN		(0x1L<<0)	/* Bit 0:	Address Decode enable */

/* Device Dependent Region */
/*	PCI_OUR_REG_1		32 bit	Our Register 1 */
									/* Bit 31..26:	reserved */
#define PCI_VIO			(1L<<25)	/* Bit 25:	PCI IO Voltage, */
									/*		0 = 3.3V / 1 = 5V */
#define	PCI_EN_BOOT		(1L<<24)	/* Bit 24:	Enable BOOT via ROM */
									/*		1 = Don't boot wth ROM*/
									/*		0 = Boot with ROM */
#define	PCI_EN_IO		(1L<<23)	/* Bit 23:	Mapping to IO space */
#define	PCI_EN_FPROM	(1L<<22)	/* Bit 22:	FLASH mapped to mem? */
									/*		1 = Map Flash to Mem */
									/*		0 = Disable addr. dec*/
#define	PCI_PAGESIZE	(3L<<20)	/* Bit 21..20:	FLASH Page Size	*/
#define	PCI_PAGE_16		(0L<<20)	/*		16 k pages	*/
#define	PCI_PAGE_32K	(1L<<20)	/*		32 k pages	*/
#define	PCI_PAGE_64K	(2L<<20)	/*		64 k pages	*/
#define	PCI_PAGE_128K	(3L<<20)	/*		128 k pages	*/
									/* Bit 19:	reserved	*/
#define	PCI_PAGEREG		(7L<<16)	/* Bit 18..16:	Page Register	*/
#define PCI_NOTAR		(1L<<15)	/* Bit 15:	No turnaround cycle */
#define	PCI_FORCE_BE	(1L<<14)	/* Bit 14:	Assert all BEs on MR */
#define	PCI_DIS_MRL		(1L<<13)	/* Bit 13:	Disable Mem R Line */
#define	PCI_DIS_MRM		(1L<<12)	/* Bit 12:	Disable Mem R multip */
#define	PCI_DIS_MWI		(1L<<11)	/* Bit 11:	Disable Mem W & inv */
#define	PCI_DISC_CLS	(1L<<10)	/* Bit 10:	Disc: cacheLsz bound */
#define	PCI_BURST_DIS	(1L<<9)		/* Bit	9:	Burst Disable */
#define	PCI_DIS_PCI_CLK	(1L<<8)		/* Bit	8:	Disable PCI clock driv*/
#define	PCI_SKEW_DAS	(0xfL<<4)	/* Bit	7..4:	Skew Ctrl, DAS Ext */
#define	PCI_SKEW_BASE	(0xfL<<0)	/* Bit	3..0:	Skew Ctrl, Base	*/


/*	PCI_OUR_REG_2		32 bit	Our Register 2 */
#define PCI_VPD_WR_THR	(0xffL<<24)	/* Bit 31..24:	VPD Write Threshold */
#define	PCI_DEV_SEL		(0x7fL<<17)	/* Bit 23..17:	EEPROM Device Select */
#define	PCI_VPD_ROM_SZ	(7L<<14)	/* Bit 16..14:	VPD ROM Size	*/
									/* Bit 13..12:	reserved	*/
#define	PCI_PATCH_DIR	(0xfL<<8)	/* Bit 11.. 8:	Ext Patchs dir 3..0 */
#define	PCI_PATCH_DIR_0	(1L<<8)
#define	PCI_PATCH_DIR_1	(1L<<9)
#define	PCI_PATCH_DIR_2	(1L<<10)
#define	PCI_PATCH_DIR_3	(1L<<11)
#define PCI_EXT_PATCHS	(0xfL<<4)	/* Bit	7..4:	Extended Patches 3..0 */
#define	PCI_EXT_PATCH_0	(1L<<4)
#define	PCI_EXT_PATCH_1	(1L<<5)
#define	PCI_EXT_PATCH_2	(1L<<6)
#define	PCI_EXT_PATCH_3	(1L<<7)
#define	PCI_EN_DUMMY_RD	(1L<<3)		/* Bit	3:	Enable Dummy Read */
#define PCI_REV_DESC	(1L<<2)		/* Bit	2:	Reverse Desc. Bytes */
									/* Bit	1:	reserved */
#define PCI_USEDATA64	(1L<<0)		/* Bit	0:	Use 64Bit Data bus ext*/


/* Power Management Region */
/*	PCI_PM_CAP_REG		16 bit	Power Management Capabilities */
#define	PCI_PME_SUP		(0x1f<<11)	/* Bit 15..11:	PM Manag. Event Sup */
#define PCI_PM_D2_SUB	(1<<10)		/* Bit 10:	D2 Support Bit */
#define PCI_PM_D1_SUB	(1<<9)		/* Bit	9:	D1 Support Bit */
									/* Bit	8..6:	reserved */
#define PCI_PM_DSI		(1<<5)		/* Bit	5:	Device Specific Init.*/
#define PCI_PM_APS		(1<<4)		/* Bit	4:	Auxialiary Power Src */
#define PCI_PME_CLOCK	(1<<3)		/* Bit	3:	PM Event Clock */
#define PCI_PM_VER		(7<<0)		/* Bit	2..0:	PM PCI Spec. version */

/*	PCI_PM_CTL_STS		16 bit	Power Manag. Control/Status */
#define	PCI_PME_STATUS	(1<<15)		/* Bit 15: 	PGA doesn't sup. PME# */
#define PCI_PM_DAT_SCL	(3<<13)		/* Bit 14..13:	dat reg Scaling factor*/
#define PCI_PM_DAT_SEL	(0xf<<9)	/* Bit 12.. 9:	PM data selector field*/
#define PCI_PME_EN		(1<<8)		/* Bit	8:	PGA doesn't sup. PME# */
									/* Bit	7.. 2:	reserved */
#define PCI_PM_STATE	(3<<0)		/* Bit	1.. 0:	Power Management State*/
#define PCI_PM_STATE_D0	(0<<0)		/* D0:	Operational (default) */
#define	PCI_PM_STATE_D1	(1<<0)		/* D1:	not supported */
#define PCI_PM_STATE_D2	(2<<0)		/* D2:	not supported */
#define PCI_PM_STATE_D3 (3<<0)		/* D3:	HOT, Power Down and Reset */

/* VPD Region */
/*	PCI_VPD_ADR_REG		16 bit	VPD Address Register */
#define	PCI_VPD_FLAG	(1L<<15)	/* Bit 15:	starts VPD rd/wd cycle*/
#define PCI_VPD_ADDR	(0x3fffL<<0)	/* Bit 14..0:	VPD address */

/*
 *	Control Register File:
 *	Bank 0
 */
#define	B0_RAP			0x0000	/*  8 bit	Register Address Port */
	/* 0x0001 - 0x0003:	reserved */
#define	B0_CTST			0x0004	/* 16 bit	Control/Status register */
#define	B0_LED			0x0006	/*  8 Bit	LED register */
	/* 0x0007:		reserved */
#define	B0_ISRC			0x0008	/* 32 bit	Interrupt Source Register */
#define	B0_IMSK			0x000c	/* 32 bit	Interrupt Mask Register */
#define B0_HWE_ISRC		0x0010	/* 32 bit	HW Error Interrupt Src Reg */
#define B0_HWE_IMSK		0x0014	/* 32 bit	HW Error Interrupt Mask Reg */
#define B0_SP_ISRC		0x0018	/* 32 bit	Special Interrupt Source Reg */
	/* 0x001c:		reserved */

/* B0 XMAC 1 registers */
#define	B0_XM1_IMSK		0x0020	/* 16 bit r/w	XMAC 1 Interrupt Mask Register*/
	/* 0x0022 - 0x0027	reserved */
#define B0_XM1_ISRC		0x0028	/* 16 bit ro	XMAC 1 Interrupt Status Reg */
	/* 0x002a - 0x002f	reserved */
#define B0_XM1_PHY_ADDR 0x0030	/* 16 bit r/w	XMAC 1 PHY Address Register */
	/* 0x0032 - 0x0033	reserved */
#define B0_XM1_PHY_DATA 0x0034	/* 16 bit r/w	XMAC 1 PHY Data Register */
	/* 0x0036 - 0x003f	reserved */

/* B0 XMAC 2 registers */
#define	B0_XM2_IMSK		0x0040	/* 16 bit r/w	XMAC 2 Interrupt Mask Register*/
	/* 0x0042 - 0x0047	reserved */
#define B0_XM2_ISRC		0x0048	/* 16 bit ro	XMAC 2 Interrupt Status Reg */
	/* 0x004a - 0x004f	reserved */
#define B0_XM2_PHY_ADDR 0x0050	/* 16 bit r/w	XMAC 2 PHY Address Register */
	/* 0x0052 - 0x0053	reserved */
#define B0_XM2_PHY_DATA 0x0054	/* 16 bit r/w	XMAC 2 PHY Data Register */
				/* 0x0056 - 0x005f	reserved */

/* BMU Control Status Registers */
#define	B0_R1_CSR		0x0060	/* 32 bit	BMU Ctrl/Stat Rx Queue 1 */
#define	B0_R2_CSR		0x0064	/* 32 bit	BMU Ctrl/Stat Rx Queue 2 */
#define	B0_XS1_CSR		0x0068	/* 32 bit	BMU Ctrl/Stat Sync Tx Queue 1 */
#define	B0_XA1_CSR		0x006c	/* 32 bit	BMU Ctrl/Stat Async Tx Queue 1*/
#define	B0_XS2_CSR		0x0070	/* 32 bit	BMU Ctrl/Stat Sync Tx Queue 2 */
#define	B0_XA2_CSR		0x0074	/* 32 bit	BMU Ctrl/Stat Async Tx Queue 2*/
	/* x0078 - 0x007f	reserved */

/*
 *	Bank 1
 *	- completely empty (this is the RAP Block window)
 *	Note: if RAP = 1 this page is reserved
 */

/*
 *	Bank 2
 */
/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */

#define	B2_MAC_1		0x0100	/* NA reg	 MAC Address 1 */
	/* 0x0106 - 0x0107	reserved */
#define	B2_MAC_2		0x0108	/* NA reg	 MAC Address 2 */
	/* 0x010e - 0x010f	reserved */
#define	B2_MAC_3		0x0110	/* NA reg	 MAC Address 3 */
	/* 0x0116 - 0x0117	reserved */
#define B2_CONN_TYP		0x0118	/*  8 bit	Connector type */
#define B2_PMD_TYP		0x0119	/*  8 bit	PMD type */
#define B2_MAC_CFG		0x011a	/*  8 bit	MAC Configuration */
#define B2_CHIP_REV		0x011b	/*  8 bit 	Queen Chip Revision Number */
	/* Eprom registers are currently of no use */
#define B2_E_0			0x011c	/*  8 bit	EPROM Byte 0 */
#define B2_E_1			0x011d	/*  8 bit	EPROM Byte 1 */
#define B2_E_2			0x011e	/*  8 bit	EPROM Byte 2 */
#define B2_E_3			0x011f	/*  8 bit	EPROM Byte 3 */
#define B2_FAR			0x0120	/* 32 bit	Flash-Prom Addr Reg/Cnt */
#define B2_FDP			0x0124	/*  8 bit	Flash-Prom Data Port */
	/* 0x0125 - 0x0127:	reserved */
#define B2_LD_CRTL		0x0128	/*  8 bit	EPROM loader control register */
#define B2_LD_TEST		0x0129	/*  8 bit	EPROM loader test register */
	/* 0x012a - 0x012f:	reserved */
#define B2_TI_INI		0x0130	/* 32 bit	Timer init value */
#define B2_TI_VAL		0x0134	/* 32 bit	Timer value */
#define B2_TI_CRTL		0x0138	/*  8 bit	Timer control */
#define B2_TI_TEST		0x0139	/*  8 Bit	Timer Test */
	/* 0x013a - 0x013f:	reserved */
#define B2_IRQM_INI		0x0140	/* 32 bit	IRQ Moderation Timer Init Reg.*/
#define B2_IRQM_VAL		0x0144	/* 32 bit	IRQ Moderation Timer Value */
#define B2_IRQM_CTRL	0x0148	/*  8 bit	IRQ Moderation Timer Control */
#define B2_IRQM_TEST	0x0149	/*  8 bit	IRQ Moderation Timer Test */
#define B2_IRQM_MSK 	0x014c	/* 32 bit	IRQ Moderation Mask */
#define B2_IRQM_HWE_MSK 0x0150	/* 32 bit	IRQ Moderation HW Error Mask */
	/* 0x0154 - 0x0157:	reserved */
#define	B2_TST_CTRL1	0x0158	/*  8 bit	Test Control Register 1 */
#define B2_TST_CTRL2	0x0159	/*  8 bit	Test Control Register 2 */
	/* 0x015a - 0x015b:	reserved */
#define B2_GP_IO		0x015c	/* 32 bit	General Purpose IO Register */
#define B2_I2C_CTRL		0x0160	/* 32 bit	I2C HW Control Register */
#define B2_I2C_DATA		0x0164	/* 32 bit	I2C HW Data Register */
#define B2_I2C_IRQ		0x0168	/* 32 bit	I2C HW IRQ Register */
#define B2_I2C_SW		0x016c	/* 32 bit	I2C SW Port Register */
#define B2_BSC_INI		0x0170	/* 32 bit	Blink Source Counter Init Val */
#define B2_BSC_VAL		0x0174	/* 32 bit	Blink Source Counter Value */
#define B2_BSC_CTRL		0x0178	/*  8 bit	Blink Source Counter Control */
#define B2_BSC_STAT		0x0179	/*  8 bit	Blink Source Counter Status */
#define B2_BSC_TST		0x017a	/* 16 bit	Blink Source Counter Test Reg */
	/* 0x017c - 0x017f:	reserved */

/*
 *	Bank 3
 */
#define B3_RAM_ADDR		0x0180	/* 32 bit	RAM Address, to read or write */
#define B3_RAM_DATA_LO	0x0184	/* 32 bit	RAM Data Word (low dWord) */
#define B3_RAM_DATA_HI	0x0188	/* 32 bit	RAM Data Word (high dWord) */
	/* 0x018c - 0x018f:	reserved */
/* RAM Interface Registers */
/*
 * The HW-Spec. call this registers Timeout Value 0..11. But this names are
 * not usable in SW. Please notice these are NOT real timeouts, these are
 * the number of qWords transfered continously.
 */
#define B3_RI_WTO_R1	0x0190	/* 8 bit RAM Iface WR Timeout Queue R1	(TO0) */
#define B3_RI_WTO_XA1	0x0191	/* 8 bit RAM Iface WR Timeout Queue XA1	(TO1) */
#define B3_RI_WTO_XS1	0x0192	/* 8 bit RAM Iface WR Timeout Queue XS1 (TO2) */
#define B3_RI_RTO_R1	0x0193	/* 8 bit RAM Iface RD Timeout Queue R1	(TO3) */
#define B3_RI_RTO_XA1	0x0194	/* 8 bit RAM Iface RD Timeout Queue XA1	(TO4) */
#define B3_RI_RTO_XS1	0x0195	/* 8 bit RAM Iface RD Timeout Queue XS1	(TO5) */
#define B3_RI_WTO_R2	0x0196	/* 8 bit RAM Iface WR Timeout Queue R2	(TO6) */
#define B3_RI_WTO_XA2	0x0197	/* 8 bit RAM Iface WR Timeout Queue XA2	(TO7) */
#define B3_RI_WTO_XS2	0x0198	/* 8 bit RAM Iface WR Timeout Queue XS2	(TO8) */
#define B3_RI_RTO_R2	0x0199	/* 8 bit RAM Iface RD Timeout Queue R2	(TO9) */
#define B3_RI_RTO_XA2	0x019a	/* 8 bit RAM Iface RD Timeout Queue XA2	(TO10)*/
#define B3_RI_RTO_XS2	0x019b	/* 8 bit RAM Iface RD Timeout Queue XS2	(TO11)*/
#define B3_RI_TO_VAL	0x019c	/* 8 bit RAM Iface Current Timeout Count Val */
	/* 0x019d - 0x019f	reserved */
#define B3_RI_CTRL		0x01a0	/* 16 bit	RAM Iface Control Register */
#define B3_RI_TEST		0x01a2	/*  8 bit	RAM Iface Test Register */
	/* 0x01a3 - 0x01af	reserved */
/* MAC Arbiter Registers */
/* Please notice these are the number of qWord tranfered continously and */
/* NOT real timeouts */
#define B3_MA_TOINI_RX1	0x01b0	/* 8 bit Timeout Init Value Rx Path MAC 1 */
#define B3_MA_TOINI_RX2	0x01b1	/* 8 bit Timeout Init Value Rx Path MAC 2 */
#define B3_MA_TOINI_TX1	0x01b2	/* 8 bit Timeout Init Value Tx Path MAC 1 */
#define B3_MA_TOINI_TX2	0x01b3	/* 8 bit Timeout Init Value Tx Path MAC 2 */
#define B3_MA_TOVAL_RX1	0x01b4	/* 8 bit Timeout Value Rx Path MAC 1 */
#define B3_MA_TOVAL_RX2	0x01b5	/* 8 bit Timeout Value Rx Path MAC 1 */
#define B3_MA_TOVAL_TX1	0x01b6	/* 8 bit Timeout Value Tx Path MAC 2 */
#define B3_MA_TOVAL_TX2	0x01b7	/* 8 bit Timeout Value Tx Path MAC 2 */
#define B3_MA_TO_CTRL	0x01b8	/* 16 bit	MAC Arbiter Timeout Ctrl Reg */
#define B3_MA_TO_TEST	0x01ba	/* 16 bit	MAC Arbiter Timeout Test Reg */
	/* 0x01bc - 0x01bf	reserved */
#define B3_MA_RCINI_RX1	0x01c0	/* 8 bit Recovery Init Value Rx Path MAC 1 */
#define B3_MA_RCINI_RX2	0x01c1	/* 8 bit Recovery Init Value Rx Path MAC 2 */
#define B3_MA_RCINI_TX1	0x01c2	/* 8 bit Recovery Init Value Tx Path MAC 1 */
#define B3_MA_RCINI_TX2	0x01c3	/* 8 bit Recovery Init Value Tx Path MAC 2 */
#define B3_MA_RCVAL_RX1	0x01c4	/* 8 bit Recovery Value Rx Path MAC 1 */
#define B3_MA_RCVAL_RX2	0x01c5	/* 8 bit Recovery Value Rx Path MAC 1 */
#define B3_MA_RCVAL_TX1	0x01c6	/* 8 bit Recovery Value Tx Path MAC 2 */
#define B3_MA_RCVAL_TX2	0x01c7	/* 8 bit Recovery Value Tx Path MAC 2 */
#define B3_MA_RC_CTRL	0x01c8	/* 16 bit	MAC Arbiter Recovery Ctrl Reg */
#define B3_MA_RC_TEST	0x01ca	/* 16 bit	MAC Arbiter Recovery Test Reg */
	/* 0x01cc - 0x01cf	reserved */
/* Packet Arbiter Registers, This are real timeouts */
#define B3_PA_TOINI_RX1	0x01d0	/* 16 bit	Timeout Init Val Rx Path MAC 1*/
	/* 0x01d2 - 0x01d3:	reserved */
#define B3_PA_TOINI_RX2	0x01d4	/* 16 bit	Timeout Init Val Rx Path MAC 2*/
	/* 0x01d6 - 0x01d7:	reserved */
#define B3_PA_TOINI_TX1	0x01d8	/* 16 bit	Timeout Init Val Tx Path MAC 1*/
	/* 0x01da - 0x01db:	reserved */
#define B3_PA_TOINI_TX2	0x01dc	/* 16 bit	Timeout Init Val Tx Path MAC 2*/
	/* 0x01de - 0x01df:	reserved */
#define B3_PA_TOVAL_RX1	0x01e0	/* 16 bit	Timeout Val Rx Path MAC 1 */
	/* 0x01e2 - 0x01e3:	reserved */
#define B3_PA_TOVAL_RX2	0x01e4	/* 16 bit	Timeout Val Rx Path MAC 2 */
	/* 0x01e6 - 0x01e7:	reserved */
#define B3_PA_TOVAL_TX1	0x01e8	/* 16 bit	Timeout Val Tx Path MAC 1 */
	/* 0x01ea - 0x01eb:	reserved */
#define B3_PA_TOVAL_TX2	0x01ec	/* 16 bit	Timeout Val Tx Path MAC 2 */
	/* 0x01ee - 0x01ef:	reserved */
#define B3_PA_CTRL	0x01f0	/* 16 bit	Packet Arbiter Ctrl Register */
#define B3_PA_TEST	0x01f2	/* 16 bit	Packet Arbiter Test Register */
	/* 0x01f4 - 0x01ff:	reserved */

/*
 *	Bank 4 - 5
 */

/* Transmit Arbiter Registers MAC 1 and 2, user MR_ADDR() to address */
#define TXA_ITI_INI		0x0200	/* 32 bit	Tx Arb Interval Timer Init Val*/
#define TXA_ITI_VAL		0x0204	/* 32 bit	Tx Arb Interval Timer Value */
#define TXA_LIM_INI		0x0208	/* 32 bit	Tx Arb Limit Counter Init Val */
#define TXA_LIM_VAL		0x020c	/* 32 bit	Tx Arb Limit Counter Value */
#define TXA_CTRL		0x0210	/*  8 bit	Tx Arbiter Control Register */
#define TXA_TEST		0x0211	/*  8 bit	Tx Arbiter Test Register */
#define TXA_STAT		0x0212	/*  8 bit	Tx Arbiter Status Register */
	/* 0x0213 - 0x027f:	reserved */

/*
 *	Bank 6