xmac_ii.h

移植到2410开发板上的源代码

/*----------------------------------------------------------------------------*/
/*
 * XMAC-PHY Registers, indirect addressed over the XMAC
 */
#define	PHY_XMAC_CTRL		0x00	/* 16 bit r/w	PHY Control Register */
#define	PHY_XMAC_STAT		0x01	/* 16 bit r/w	PHY Status Register */
#define	PHY_XMAC_ID0		0x02	/* 16 bit ro	PHY ID0 Register */
#define	PHY_XMAC_ID1		0x03	/* 16 bit ro	PHY ID1 Register */
#define	PHY_XMAC_AUNE_ADV	0x04	/* 16 bit r/w	Autoneg Advertisement */
#define	PHY_XMAC_AUNE_LP	0x05	/* 16 bit ro	Link Partner Abi Reg */
#define	PHY_XMAC_AUNE_EXP	0x06	/* 16 bit ro	Autoneg Expansion Reg */
#define	PHY_XMAC_NEPG		0x07	/* 16 bit r/w	Next Page Register */
#define	PHY_XMAC_NEPG_LP	0x08	/* 16 bit ro	Next Page Link P Reg */
	/* 0x09 - 0x0e:		reserved */
#define	PHY_XMAC_EXT_STAT	0x0f	/* 16 bit ro	Ext Status Register */
#define	PHY_XMAC_RES_ABI	0x10	/* 16 bit ro	PHY Resolved Ability */

/*----------------------------------------------------------------------------*/
/*
 * Broadcom-PHY Registers, indirect addressed over XMAC
 */
#define	PHY_BCOM_CTRL		0x00	/* 16 bit r/w	PHY Control Register */
#define	PHY_BCOM_STAT		0x01	/* 16 bit ro	PHY Status Register */
#define	PHY_BCOM_ID0		0x02	/* 16 bit ro	PHY ID0 Register */
#define	PHY_BCOM_ID1		0x03	/* 16 bit ro	PHY ID1 Register */
#define	PHY_BCOM_AUNE_ADV	0x04	/* 16 bit r/w	Autoneg Advertisement */
#define	PHY_BCOM_AUNE_LP	0x05	/* 16 bit ro	Link Part Ability Reg */
#define	PHY_BCOM_AUNE_EXP	0x06	/* 16 bit ro	Autoneg Expansion Reg */
#define	PHY_BCOM_NEPG		0x07	/* 16 bit r/w	Next Page Register */
#define	PHY_BCOM_NEPG_LP	0x08	/* 16 bit ro	Next Page Link P Reg */
	/* Broadcom-specific registers */
#define	PHY_BCOM_1000T_CTRL	0x09	/* 16 bit r/w	1000Base-T Ctrl Reg */
#define	PHY_BCOM_1000T_STAT	0x0a	/* 16 bit ro	1000Base-T Status Reg */
	/* 0x0b - 0x0e:		reserved */
#define	PHY_BCOM_EXT_STAT	0x0f	/* 16 bit ro	Extended Status Reg */
#define	PHY_BCOM_P_EXT_CTRL	0x10	/* 16 bit r/w	PHY Extended Ctrl Reg */
#define	PHY_BCOM_P_EXT_STAT	0x11	/* 16 bit ro	PHY Extended Stat Reg */
#define	PHY_BCOM_RE_CTR		0x12	/* 16 bit r/w	Receive Error Counter */
#define	PHY_BCOM_FC_CTR		0x13	/* 16 bit r/w	False Carr Sense Cnt */
#define	PHY_BCOM_RNO_CTR	0x14	/* 16 bit r/w	Receiver NOT_OK Cnt */
	/* 0x15 - 0x17:		reserved */
#define	PHY_BCOM_AUX_CTRL	0x18	/* 16 bit r/w	Auxiliary Control Reg */
#define	PHY_BCOM_AUX_STAT	0x19	/* 16 bit ro	Auxiliary Stat Summary*/
#define	PHY_BCOM_INT_STAT	0x1a	/* 16 bit ro	Interrupt Status Reg */
#define	PHY_BCOM_INT_MASK	0x1b	/* 16 bit r/w	Interrupt Mask Reg */
	/* 0x1c:		reserved */
	/* 0x1d - 0x1f:		test registers */

/*----------------------------------------------------------------------------*/
/*
 * Level One-PHY Registers, indirect addressed over XMAC
 */
#define	PHY_LONE_CTRL		0x00	/* 16 bit r/w	PHY Control Register */
#define	PHY_LONE_STAT		0x01	/* 16 bit ro	PHY Status Register */
#define	PHY_LONE_ID0		0x02	/* 16 bit ro	PHY ID0 Register */
#define	PHY_LONE_ID1		0x03	/* 16 bit ro	PHY ID1 Register */
#define	PHY_LONE_AUNE_ADV	0x04	/* 16 bit r/w	Autoneg Advertisement */
#define	PHY_LONE_AUNE_LP	0x05	/* 16 bit ro	Link Part Ability Reg */
#define	PHY_LONE_AUNE_EXP	0x06	/* 16 bit ro	Autoneg Expansion Reg */
#define	PHY_LONE_NEPG		0x07	/* 16 bit r/w	Next Page Register */
#define	PHY_LONE_NEPG_LP	0x08	/* 16 bit ro	Next Page Link Partner*/
	/* Level One-specific registers */
#define	PHY_LONE_1000T_CTRL	0x09	/* 16 bit r/w	1000Base-T Control Reg*/
#define	PHY_LONE_1000T_STAT	0x0a	/* 16 bit ro	1000Base-T Status Reg */
	/* 0x0b -0x0e:		reserved */
#define	PHY_LONE_EXT_STAT	0x0f	/* 16 bit ro	Extended Status Reg */
#define	PHY_LONE_PORT_CFG	0x10	/* 16 bit r/w	Port Configuration Reg*/
#define	PHY_LONE_Q_STAT		0x11	/* 16 bit ro	Quick Status Reg */
#define	PHY_LONE_INT_ENAB	0x12	/* 16 bit r/w	Interrupt Enable Reg */
#define	PHY_LONE_INT_STAT	0x13	/* 16 bit ro	Interrupt Status Reg */
#define	PHY_LONE_LED_CFG	0x14	/* 16 bit r/w	LED Configuration Reg */
#define	PHY_LONE_PORT_CTRL	0x15	/* 16 bit r/w	Port Control Reg */
#define	PHY_LONE_CIM		0x16	/* 16 bit ro	CIM Reg */
	/* 0x17 -0x1c:		reserved */

/*----------------------------------------------------------------------------*/
/*
 * National-PHY Registers, indirect addressed over XMAC
 */
#define	PHY_NAT_CTRL		0x00	/* 16 bit r/w	PHY Control Register */
#define	PHY_NAT_STAT		0x01	/* 16 bit r/w	PHY Status Register */
#define	PHY_NAT_ID0			0x02	/* 16 bit ro	PHY ID0 Register */
#define	PHY_NAT_ID1			0x03	/* 16 bit ro	PHY ID1 Register */
#define	PHY_NAT_AUNE_ADV	0x04	/* 16 bit r/w	Autonegotiation Advertisement */
#define	PHY_NAT_AUNE_LP		0x05	/* 16 bit ro	Link Partner Ability Reg */
#define	PHY_NAT_AUNE_EXP	0x06	/* 16 bit ro	Autonegotiation Expansion Reg */
#define	PHY_NAT_NEPG		0x07	/* 16 bit r/w	Next Page Register */
#define	PHY_NAT_NEPG_LP		0x08	/* 16 bit ro	Next Page Link Partner Reg */
	/* National-specific registers */
#define	PHY_NAT_1000T_CTRL	0x09	/* 16 bit r/w	1000Base-T Control Reg */
#define	PHY_NAT_1000T_STAT	0x0a	/* 16 bit ro	1000Base-T Status Reg */
	/* 0x0b -0x0e:		reserved */
#define	PHY_NAT_EXT_STAT	0x0f	/* 16 bit ro	Extended Status Register */
#define	PHY_NAT_EXT_CTRL1	0x10	/* 16 bit ro	Extended Control Reg1 */
#define	PHY_NAT_Q_STAT1		0x11	/* 16 bit ro	Quick Status Reg1 */
#define	PHY_NAT_10B_OP		0x12	/* 16 bit ro	10Base-T Operations Reg */
#define	PHY_NAT_EXT_CTRL2	0x13	/* 16 bit ro	Extended Control Reg1 */
#define	PHY_NAT_Q_STAT2		0x14	/* 16 bit ro	Quick Status Reg2 */
	/* 0x15 -0x18:		reserved */
#define	PHY_NAT_PHY_ADDR	0x19	/* 16 bit ro	PHY Address Register */


/*----------------------------------------------------------------------------*/

/*
 * PHY bit definitions
 * Bits defined as PHY_X_..., PHY_B_..., PHY_L_... or PHY_N_... are
 * Xmac/Broadcom/LevelOne/National-specific.
 * All other are general.
 */

/*****	PHY_XMAC_CTRL	16 bit r/w	PHY Control Register *****/
/*****	PHY_BCOM_CTRL	16 bit r/w	PHY Control Register *****/
/*****	PHY_LONE_CTRL	16 bit r/w	PHY Control Register *****/
#define	PHY_CT_RESET	(1<<15)	/* Bit 15: (sc)	clear all PHY releated regs */
#define PHY_CT_LOOP		(1<<14)	/* Bit 14:	enable Loopback over PHY */
#define PHY_CT_SPS_LSB	(1<<13) /* Bit 13: (BC,L1) Speed select, lower bit */
#define PHY_CT_ANE		(1<<12)	/* Bit 12:	Autonegotiation Enabled */
#define PHY_CT_PDOWN	(1<<11)	/* Bit 11: (BC,L1) Power Down Mode */
#define PHY_CT_ISOL		(1<<10)	/* Bit 10: (BC,L1) Isolate Mode */
#define PHY_CT_RE_CFG	(1<<9)	/* Bit	9: (sc) Restart Autonegotiation */
#define PHY_CT_DUP_MD	(1<<8)	/* Bit	8:	Duplex Mode */
#define PHY_CT_COL_TST	(1<<7)	/* Bit	7: (BC,L1) Collsion Test enabled */
#define PHY_CT_SPS_MSB	(1<<6)	/* Bit	6: (BC,L1) Speed select, upper bit */
								/* Bit	5..0:	reserved */

#define PHY_B_CT_SP1000	(1<<6)	/* Bit  6:	enable speed of 1000 MBit/s */
#define PHY_B_CT_SP100	(1<<13)	/* Bit 13:	enable speed of  100 MBit/s */
#define PHY_B_CT_SP10	(0)	/* Bit 6/13 not set,	speed of  10 MBit/s */

#define PHY_L_CT_SP1000	(1<<6)	/* Bit  6:      enable speed of 1000 MBit/s */
#define PHY_L_CT_SP100	(1<<13)	/* Bit 13:      enable speed of  100 MBit/s */
#define PHY_L_CT_SP10	(0)	/* Bit 6/13 not set,    speed of  10 MBit/s */


/*****	PHY_XMAC_STAT	16 bit r/w	PHY Status Register *****/
/*****	PHY_BCOM_STAT	16 bit r/w	PHY Status Register *****/
/*****	PHY_LONE_STAT	16 bit r/w	PHY Status Register *****/
								/* Bit 15..9:	reserved */
				/*	(BC/L1) 100/10 MBit/s cap bits ignored*/
#define PHY_ST_EXT_ST	(1<<8)	/* Bit	8:	Extended Status Present */
								/* Bit	7:	reserved */
#define PHY_ST_PRE_SUB	(1<<6)	/* Bit	6: (BC/L1) preamble suppression */
#define PHY_ST_AN_OVER	(1<<5)	/* Bit	5:	Autonegotiation Over */
#define PHY_ST_REM_FLT	(1<<4)	/* Bit	4:	Remode Fault Condition Occured*/
#define PHY_ST_AN_CAP	(1<<3)	/* Bit	3:	Autonegotiation Capability */
#define PHY_ST_LSYNC	(1<<2)	/* Bit	2:	Link Synchronized */
#define PHY_ST_JAP_DET	(1<<1)	/* Bit	1: (BC/L1) Japper Detected */
#define PHY_ST_EXT_REG	(1<<0)	/* Bit	0:	Extended Register available */


/*	PHY_XMAC_ID1		16 bit ro	PHY ID1 Register */
/*	PHY_BCOM_ID1		16 bit ro	PHY ID1 Register */
/*	PHY_LONE_ID1		16 bit ro	PHY ID1 Register */
#define	PHY_I1_OUI		(0x3f<<10)	/* Bit 15..10:	Organiz. Unique ID */
#define PHY_I1_MOD_NUM	(0x3f<<4)	/* Bit	9.. 4:	Model Number */
#define PHY_I1_REV		(0x0f<<0)	/* Bit	3.. 0:	Revision Number */


/*****	PHY_XMAC_AUNE_ADV	16 bit r/w	Autoneg Advertisement *****/
/*****	PHY_XMAC_AUNE_LP	16 bit ro	Link Partner Ability Reg *****/
#define PHY_AN_NXT_PG	(1<<15)	/* Bit 15:	Request Next Page */
#define PHY_X_AN_ACK	(1<<14)	/* Bit 14: (ro)	Acknowledge Received */
#define PHY_X_AN_RFB	(3<<12)	/* Bit 13..12:	Remode Fault Bits */
								/* Bit 11.. 9:	reserved */
#define PHY_X_AN_PAUSE	(3<<7)	/* Bit	8.. 7:	Pause Bits */
#define PHY_X_AN_HD		(1<<6)	/* Bit	6:	Half Duplex */
#define PHY_X_AN_FD		(1<<5)	/* Bit	5:	Full Duplex */
								/* Bit	4.. 0:	reserved */

/*****	PHY_BCOM_AUNE_ADV	16 bit r/w	Autoneg Advertisement *****/
/*****	PHY_BCOM_AUNE_LP	16 bit ro	Link Partner Ability Reg *****/
/*	PHY_AN_NXT_PG		(see XMAC) Bit 15:	Request Next Page */
								/* Bit 14:	reserved */
#define PHY_B_AN_RF		(1<<13)	/* Bit 13:	Remote Fault */
								/* Bit 12:	reserved */
#define PHY_B_AN_ASP	(1<<11)	/* Bit 11:	Asymetric Pause */
#define PHY_B_AN_PC		(1<<10)	/* Bit 10:	Pause Capable */
								/* Bit	9..5:	100/10 BT cap bits ingnored */
#define PHY_B_AN_SEL	(0x1f<<0)/* Bit 4..0:	Selector Field, 00001=Ethernet*/

/*****	PHY_LONE_AUNE_ADV	16 bit r/w	Autoneg Advertisement *****/
/*****	PHY_LONE_AUNE_LP	16 bit ro	Link Partner Ability Reg *****/
/*	PHY_AN_NXT_PG		(see XMAC) Bit 15:	Request Next Page */
								/* Bit 14:	reserved */
#define PHY_L_AN_RF		(1<<13)	/* Bit 13:	Remote Fault */
								/* Bit 12:	reserved */
#define PHY_L_AN_ASP	(1<<11)	/* Bit 11:	Asymetric Pause */
#define PHY_L_AN_PC		(1<<10)	/* Bit 10:	Pause Capable */
								/* Bit	9..5:	100/10 BT cap bits ingnored */
#define PHY_L_AN_SEL	(0x1f<<0)/* Bit 4..0:	Selector Field, 00001=Ethernet*/

/*****	PHY_NAT_AUNE_ADV	16 bit r/w	Autoneg Advertisement *****/
/*****	PHY_NAT_AUNE_LP	16 bit ro	Link Partner Ability Reg *****/
/*	PHY_AN_NXT_PG		(see XMAC) Bit 15:	Request Next Page */
								/* Bit 14:	reserved */
#define PHY_N_AN_RF		(1<<13)	/* Bit 13:	Remote Fault */
								/* Bit 12:	reserved */
#define PHY_N_AN_100F	(1<<11)	/* Bit 11:	100Base-T2 FD Support */
#define PHY_N_AN_100H	(1<<10)	/* Bit 10:	100Base-T2 HD Support */
								/* Bit	9..5:	100/10 BT cap bits ingnored */
#define PHY_N_AN_SEL	(0x1f<<0)/* Bit 4..0:	Selector Field, 00001=Ethernet*/

/* field type definition for PHY_x_AN_SEL */
#define PHY_SEL_TYPE	0x01	/* 00001 = Ethernet */

/*****	PHY_XMAC_AUNE_EXP	16 bit ro	Autoneg Expansion Reg *****/
				/* Bit 15..4:	reserved */
#define PHY_AN_LP_NP	(1<<3)	/* Bit	3:	Link Partner can Next Page */
#define PHY_AN_LOC_NP	(1<<2)	/* Bit	2:	Local PHY can Next Page */
#define PHY_AN_RX_PG	(1<<1)	/* Bit	1:	Page Received */
								/* Bit	0:	reserved */

/*****	PHY_BCOM_AUNE_EXP	16 bit ro	Autoneg Expansion Reg *****/
								/* Bit 15..5:	reserved */
#define PHY_B_AN_PDF	(1<<4)	/* Bit	4:	Parallel Detection Fault */
/*	PHY_AN_LP_NP		(see XMAC) Bit	3:	Link Partner can Next Page */
/*	PHY_AN_LOC_NP		(see XMAC) Bit	2:	Local PHY can Next Page */
/*	PHY_AN_RX_PG		(see XMAC) Bit	1:	Page Received */
#define PHY_B_AN_LP_CAP	(1<<0)	/* Bit	0:	Link Partner Autoneg Cap. */ 	

/*****	PHY_LONE_AUNE_EXP	16 bit ro	Autoneg Expansion Reg *****/
#define PHY_L_AN_BP		(1<<5)	/* Bit	5:	Base Page Indication */
#define PHY_L_AN_PDF	(1<<4)	/* Bit	4:	Parallel Detection Fault */
/*	PHY_AN_LP_NP		(see XMAC) Bit	3:	Link Partner can Next Page */
/*	PHY_AN_LOC_NP		(see XMAC) Bit	2:	Local PHY can Next Page */
/*	PHY_AN_RX_PG		(see XMAC) Bit	1:	Page Received */
#define PHY_B_AN_LP_CAP	(1<<0)	/* Bit	0:	Link Partner Autoneg Cap. */ 	


/*****	PHY_XMAC_NEPG		16 bit r/w	Next Page Register *****/
/*****	PHY_BCOM_NEPG		16 bit r/w	Next Page Register *****/
/*****	PHY_LONE_NEPG		16 bit r/w	Next Page Register *****/
/*****	PHY_XMAC_NEPG_LP	16 bit ro	Next Page Link Partner *****/
/*****	PHY_BCOM_NEPG_LP	16 bit ro	Next Page Link Partner *****/
/*****	PHY_LONE_NEPG_LP	16 bit ro	Next Page Link Partner *****/
#define PHY_NP_MORE		(1<<15)	/* Bit 15:	More, Next Pages to follow */
#define PHY_NP_ACK1		(1<<14)	/* Bit 14: (ro)	Ack 1, for receiving a message*/
#define PHY_NP_MSG_VAL	(1<<13)	/* Bit 13:	Message Page valid */
#define PHY_NP_ACK2		(1<<12)	/* Bit 12:	Ack 2, comply with msg content*/
#define PHY_NP_TOG		(1<<11)	/* Bit 11:	Toggle Bit, ensure sync */
#define PHY_NP_MSG		0x07ff	/* Bit 10..0:	Message from/to Link Partner */

/*
 * XMAC-Specific
 */
/*****	PHY_XMAC_EXT_STAT	16 bit r/w	Extended Status Register *****/
#define PHY_X_EX_FD		(1<<15)	/* Bit 15:	Device Supports Full Duplex */
#define PHY_X_EX_HD		(1<<14)	/* Bit 14:	Device Supports Half Duplex */
								/* Bit 13..0:	reserved */

/*****	PHY_XMAC_RES_ABI	16 bit ro	PHY Resolved Ability *****/
								/* Bit 15..9:	reserved */
#define PHY_X_RS_PAUSE	(3<<7)	/* Bit	8..7:	selected Pause Mode */
#define PHY_X_RS_HD		(1<<6)	/* Bit	6:	Half Duplex Mode selected */
#define PHY_X_RS_FD		(1<<5)	/* Bit	5:	Full Duplex Mode selected */
#define PHY_X_RS_ABLMIS (1<<4)	/* Bit	4:	duplex or pause cap mismatch */
#define PHY_X_RS_PAUMIS (1<<3)	/* Bit	3:	pause capability missmatch */
								/* Bit	2..0:	reserved */
/*
 * Remote Fault Bits (PHY_X_AN_RFB) encoding
 */
#define X_RFB_OK		(0<<12)	/* Bit 12..13	No errors, Link OK */
#define X_RFB_LF		(1<<12)	/* Bit 12..13	Link Failure */
#define X_RFB_OFF		(2<<12)	/* Bit 12..13	Offline */
#define X_RFB_AN_ERR	(3<<12)	/* Bit 12..13	Autonegotiation Error */

/*
 * Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding
 */
#define PHY_X_P_NO_PAUSE	(0<<7)	/* Bit	8..7:	no Pause Mode */
#define PHY_X_P_SYM_MD		(1<<7)	/* Bit	8..7:	symmetric Pause Mode */
#define PHY_X_P_ASYM_MD		(2<<7)	/* Bit	8..7:	asymmetric Pause Mode */
#define PHY_X_P_BOTH_MD		(3<<7)	/* Bit	8..7:	both Pause Mode */


/*
 * Broadcom-Specific
 */
/***** PHY_BCOM_1000T_CTRL	16 bit r/w	1000Base-T Control Reg *****/
#define PHY_B_1000C_TEST	(7<<13)	/* Bit	15..13:	Test Modes */
#define PHY_B_1000C_MSE		(1<<12)	/* Bit	12:	Master/Slave Enable */
#define PHY_B_1000C_MSC		(1<<11)	/* Bit	11:	M/S Configuration */
#define PHY_B_1000C_RD		(1<<10)	/* Bit	10:	Repeater/DTE */
#define PHY_B_1000C_AFD		(1<<9)	/* Bit	9:	Advertise Full Duplex */
#define PHY_B_1000C_AHD		(1<<8)	/* Bit	8:	Advertise Half Duplex */
									/* Bit	7..0:	reserved */

/***** PHY_BCOM_1000T_STAT	16 bit ro	1000Base-T Status Reg *****/
#define PHY_B_1000S_MSF		(1<<15)	/* Bit	15:	Master/Slave Fault */
#define PHY_B_1000S_MSR		(1<<14)	/* Bit	14:	Master/Slave Result */