91x_init.s

ARM9 str912库源代码 所有的外设驱动

                   exception is entered.
* Input          : none
* Output         : none
*******************************************************************************/

AbortHandler:
        SUB    lr,lr,#8       /*; Update the link register.*/
        SaveContext r0,r12    /*; Save the workspace plus the current*/
                              /*; return address lr_ abt and spsr_abt.*/
       ldr r0,=Abort_Handler
       ldr lr,=Abort_Handler_end
       bx r0                 /*; Branch to Abort_Handler.*/

Abort_Handler_end:

        RestoreContext r0,r12 /*; Return to the instruction following that...*/
                              /*; ...has generated the data abort exception.*/
/*******************************************************************************
* Function Name  : IRQHandler
* Description    : This function called when IRQ exception is entered.
* Input          : none
* Output         : none
*******************************************************************************/

IRQHandler:
      SUB    lr, lr, #4				   /* Update the link register */
SaveContext r0, r12				/* Save the workspace plus the current */
										/* return address lr_irq and spsr_irq */
      LDR    r0, =VIC0VECT
      LDR    r0, [r0]					/* Read the routine address */
      LDR    r1, =VIC1VECT
      LDR    r1, [r1]
    /* Padding between the acknowledge and re-enable of interrupts */
    /* For more details, please refer to the following URL */
    /* http://www.arm.com/support/faqip/3682.html */
      NOP
      NOP
      MSR    cpsr_c,#0x1F            /*; Switch to SYS mode and enable IRQ*/
      STMFD  sp!,{lr}                /*; Save the link register.*/
      LDR    lr, =ReturnAddress 	  /*; Read the return address.*/
      BX     r0                      /*; Branch to the IRQ handler.*/
ReturnAddress:
      LDMFD	sp!, {lr}						/* Restore the link register. */
      MSR		cpsr_c, #Mode_IRQ|I_Bit|F_Bit	/* Switch to IRQ mode and disable IRQ */
      LDR		r0, =VIC0VECT			/* Write to the VectorAddress to clear the */
      STR		r0, [r0]				   /* respective interrupt in the internal interrupt */
      LDR		r1, =VIC1VECT			/* Write to the VectorAddressDaisy to clear the */
      STR		r1, [r1]				   /* respective interrupt in the internal interrupt */
RestoreContext r0, r12			/* Restore the context and return to the program execution. */

/******************************************************************************
;*
;*
;* Description    : Startup Code (executed after Reset) 
;*
;*****************************************************************************/

_start:
		LDR     pc, =NextInst
NextInst:

		NOP		/* Wait for OSC stabilization */
		NOP
		NOP
		NOP
		NOP
		NOP
		NOP
		NOP
		NOP





  /*; -------------------------------------------------------------------------------------------------
	; Description  :   Enable the Buffered mode.
	;                 Just enable the buffered define on the 91x_conf.h
	;		      http://www.arm.com/pdfs/DDI0164A_966E_S.pdf 
	; -------------------------------------------------------------------------------------------------*/

      MRC     p15, 0, r0, c1, c0, 0   /*; Read CP15 register 1 into r0*/
      ORR     r0, r0, #0x8            /*; Enable Write Buffer on AHB*/
      MCR     p15, 0, r0, c1, c0, 0   /*; Write CP15 register 1*/




/* Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, */
/* when the bank 0 is the boot bank, then enable the Bank 1. */

		LDR		r0, =FMI_BASE_UMB
		
		LDR		r1, =_bb_size			/* configure 512KB Boot bank 0 */
		STR		r1, [r0, #BBSR_off_addr]

		
		LDR		r1, =_nbb_size			/* configure 32KB Non Boot bank 1 */
		STR		r1, [r0, #NBBSR_off_addr]
		
		
		LDR		r1, =(0x00000000 >> 2)		/* Boot Bank Base Address 0x0 */
		STR		r1, [r0, #BBADR_off_addr]

		
		LDR		r1, =_nbb_addr		/* Non Boot Bank Base Address 0x20000  ;The Flash Bank address NBBADDR[23:0] is a word address and is mapped to CPU core address A[25:2].*/
		STR		r1, [r0, #NBBADR_off_addr]
	
		
		LDR		r1, =0x18					/*Bit 3:B0EN: Flash Bank 0 enable;Bit 4:B1EN: Flash Bank 1 enable
													; Enable CS on both banks
													STR     R7, [R6, #FMI_CR_OFST]        
													; LDR     R7, = 0x19 ;in RevD 
													; to enable 8 words PFQ deepth  */
		STR		r1, [r0, #CR_off_addr]


/* --- Enable 96K RAM, PFQBC enabled, DTCM & AHB wait-states disabled ---*/

		LDR		r0, =SCU_BASE_Address
		LDR		r1, =0x0191		
								/*System configuration register 0 (SCU_SCR0) 
								EN_PFQBC :enabled
								DTCM Wait state disable
								AHB Wait state disable 
								SRAM size(Bits 4:3):10
								SRAM_LK_EN: 0 AHB Lock transfer disabled (default)
								EMI_MUX:0: Multiplexed mode
								EMI_ALE_POLR: 1: Active high (default)
								EMI_ALE_LNGT: 1: Two clock cycles (default)
								Bits12:14 :UART_IRDA[2:0]:EXT_ETMT_EDBGR:P30_SELEDBG:
								*/
        STR     R1, [R0, #SCU_SCR0_OFST]
/*; ------------------------------------------------------------------------------
 --- System clock configuration
 ------------------------------------------------------------------------------   */

.if PLL_Clock  /*; Use 96 MHZ PLL clock as the default frequency*/
/*	.section .fastrun,"ax",%progbits
/*; --- wait states Flash confguration */

        LDR     R6, = 0x00080000            /*;Write a Write Flash Configuration */
        LDR     R7, =0x60                   /*;Register command (60h) to any word*/
        STRH    R7, [R6]                    /*;address in Bank 1.*/
 
 
        LDR     R6, = 0x00083040            /*;Write a Write Flash Configuration  */
        LDR     R7, = 0x3                   /*;Register Confirm command (03h)*/
        STRH    R7, [R6]                    /*;2Wstaites in read,PWD,LVD enabled, */
                                            /*;High BUSCFG.*/

/*; --- PLL configuration      */

        LDR     R1, = 0x00020002              /*;Set OSC as clock source*/
        STR     R1, [R0, #SCU_CLKCNTR_OFST ] 


        NOP     /*; Wait for OSC stabilization*/
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP




        LDR     R1, = 0x000ac019               /*;Set PLL ENABLE, to 96Mhz */
        STR     R1, [R0, #SCU_PLLCONF_OFST]
        
       
Wait_Loop:      
 
        LDR     R1,[R0, #SCU_SYSSTATUS_OFST]   /*;Wait until PLL is Locked*/
		  ANDS    R1, R1, #0x01 
		  BEQ     Wait_Loop
        
        
        LDR     R1, = 0x00020080             /*;Set PLL as clock source after pll */
        STR     R1, [R0, #SCU_CLKCNTR_OFST ] /*;is locked and  FMICLK=RCLK,*/
                                             /*;PCLK=RCLK/2*/

.endif


.if  RTC_Clock   /*;Use RTC  as the default clock source*/

        LDR     R1, = 0x00020001              /*;Set RTC as clock source and */
        STR     R1, [R0, #SCU_CLKCNTR_OFST ]  /*;FMICLK=RCLK, PCLK=RCLK*/
                                              
.endif


.if OSC_Clock  /*;Use Osc as the default clock source*/

        LDR     R1, = 0x00020002              /*;Set OSC as clock source  and */
        STR     R1, [R0, #SCU_CLKCNTR_OFST ]  /*;FMICLK=RCLK, PCLK=RCLK*/
                                              
.endif                                           
 
	
		
  
/* Setup Stack for each mode */

/* Enter Abort Mode and set its Stack Pointer */

		MSR		cpsr_c, #Mode_ABT|I_Bit|F_Bit
		LDR		sp, =ABT_Stack

/* Enter Undefined Instruction Mode and set its Stack Pointer */

		MSR		cpsr_c, #Mode_UND|I_Bit|F_Bit
		LDR		sp, =UNDEF_Stack

/* Enter Supervisor Mode and set its Stack Pointer */

		MSR		cpsr_c, #Mode_SVC|I_Bit|F_Bit
		LDR		sp, =_estack /*RAM_Limit*/

/* Enter FIQ Mode and set its Stack Pointer */

		MSR		cpsr_c, #Mode_FIQ|I_Bit|F_Bit
		LDR		sp, =FIQ_Stack

/* Enter IRQ Mode and set its Stack Pointer */

		MSR		cpsr_c, #Mode_IRQ|I_Bit|F_Bit
		LDR		sp, =IRQ_Stack

/* Enter System/User Mode and set its Stack Pointer */

		MSR		cpsr_c, #Mode_SYS
		LDR		sp, =USR_Stack
		
/* Set bits 17-18 (Instruction/Data TCM order) of the ARM966ES */
/* Core Configuration Control Register */
 
      MOV     r0, #0x60000
      MCR     p15,0x1,r0,c15,c1,0
		
/* Relocate .data section (Copy from FLASH to RAM) */

		LDR		r1, =_sidata
		LDR		r2, =_sdata
		LDR		r3, =_edata
LoopRel:
		CMP		r2, r3
		LDRLO	r0, [r1], #4
		STRLO	r0, [r2], #4
		BLO		LoopRel

/* Clear .bss section (Zero init) */
		MOV		r0, #0
		LDR		r1, =_sbss	
		LDR		r2, =_ebss	
LoopZI:
		CMP		r1, r2
		STRLO	r0, [r1], #4
		BLO		LoopZI

/* --- Enter the C code, use B instruction so as to never return --- */
/*    B		main														/**/

/* --- 				Now enter the C code 					             ---	*/
      ldr    PC, =main												/**/
             


	.end	

/****** (C) COPYRIGHT 2006 STMicroelectronics *********/