📄 xllp_pmu.lst
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ARM macroassembler Page:1
1 00000000 ;******************************************************************************
2 00000000 ;
3 00000000 ; COPYRIGHT (C) 2002 Intel Corporation.
4 00000000 ;
5 00000000 ; This software as well as the software described in it is furnished under
6 00000000 ; license and may only be used or copied in accordance with the terms of the
7 00000000 ; license. The information in this file is furnished for informational use
8 00000000 ; only, is subject to change without notice, and should not be construed as
9 00000000 ; a commitment by Intel Corporation. Intel Corporation assumes no
10 00000000 ; responsibility or liability for any errors or inaccuracies that may appear
11 00000000 ; in this document or any software that may be provided in association with
12 00000000 ; this document.
13 00000000 ;
14 00000000 ; Except as permitted by such license, no part of this document may be
15 00000000 ; reproduced, stored in a retrieval system, or transmitted in any form or by
16 00000000 ; any means without the express written consent of Intel Corporation.
17 00000000 ;
18 00000000 ; FILENAME: xllp_pmu.s
19 00000000 ;
20 00000000 ; PURPOSE: Provides low level PMU primitive functions written specifically for
21 00000000 ; the Bulverde/Mainstone processor/platform. Specially design to fit
22 00000000 ; into Intel VTUNE Architecture
23 00000000 ;
24 00000000 ;
25 00000000 ; LAST MODIFIED: 11/21/02
26 00000000 ;******************************************************************************
27 00000000 ;
28 00000000 ; List of primitive functions in this source code include:
29 00000000 ;
30 00000000 EXPORT XllpReadPMUReg
31 00000000 EXPORT XllpWritePMUReg
32 00000000
33 AREA |.text|, CODE, READONLY, ALIGN=5 ; Align =5 required for "ALIGN 32" to work
34 00000000
35 00000000 ;
36 00000000 ; XllpReadPMUReg - Read the PMU Register
37 00000000 ;
38 00000000 ; Description:
39 00000000 ; This routine reads the designated PMU register via CoProcesser 14.
40 00000000 ;
41 00000000 ; Input Parameters:
42 00000000 ; r0 - arg1, PMU register number to read. Number between 0 to 8
43 00000000 ; if r0 contains:
44 00000000 ; 0 -> PMNC, PMU Control Register
45 00000000 ; 1 -> CCNT, PMU Clock Counter
46 00000000 ; 2 -> PMN0, PMU Count Register 0
47 00000000 ; 3 -> PMN1, PMU Count Register 1
48 00000000 ; 4 -> PMN2, PMU Count Register 2
49 00000000 ; 5 -> PMN3, PMU Count Register 3
50 00000000 ; 6 -> INTEN, PMU Interupt Enable Register
51 00000000 ; 7 -> FLAG, PMU Overflow Flag Status Register
52 00000000 ; 8 -> EVTSEL PMU Event Select Register
53 00000000 ;
54 00000000 ; Returns:
55 00000000 ; r0 - 32-bit value read from CoProcessor
56 00000000 ;
57 00000000 ; Registers Modified:
58 00000000 ; CoProcessor Register Modified: None
59 00000000 ; General Purpose Registers Modified: r0
60 00000000 ;
61 00000000 ; NOTE:
62 00000000 ; Error checking not included
63 00000000 ;
64 00000000
65 00000000 XllpReadPMUReg FUNCTION
66 00000000
67 00000000 e3500008 cmp r0, #8
68 00000004 908ff100 addls pc, pc, r0, lsl #2
69 00000008 ea000019 b RRet
70 0000000c ea000007 b RdPMNC
71 00000010 ea000008 b RdCCNT
72 00000014 ea000009 b RdPMN0
73 00000018 ea00000a b RdPMN1
74 0000001c ea00000b b RdPMN2
75 00000020 ea00000c b RdPMN3
76 00000024 ea00000d b RdINTEN
77 00000028 ea00000e b RdFLAG
78 0000002c ea00000f b RdEVTSEL
79 00000030
80 00000030 RdPMNC
81 00000030 ee100e11 mrc p14, 0, r0, c0, c1, 0 ; Read PMNC
82 00000034 ea00000e b RRet
83 00000038 RdCCNT
84 00000038 ee110e11 mrc p14, 0, r0, c1, c1, 0 ; Read CCNT
85 0000003c ea00000c b RRet
86 00000040 RdPMN0
87 00000040 ee100e12 mrc p14, 0, r0, c0, c2, 0 ; Read PMN0
88 00000044 ea00000a b RRet
89 00000048 RdPMN1
90 00000048 ee110e12 mrc p14, 0, r0, c1, c2, 0 ; Read PMN1
91 0000004c ea000008 b RRet
92 00000050 RdPMN2
93 00000050 ee120e12 mrc p14, 0, r0, c2, c2, 0 ; Read PMN2
94 00000054 ea000006 b RRet
95 00000058 RdPMN3
96 00000058 ee130e12 mrc p14, 0, r0, c3, c2, 0 ; Read PMN3
97 0000005c ea000004 b RRet
98 00000060 RdINTEN
99 00000060 ee140e11 mrc p14, 0, r0, c4, c1, 0 ; Read INTEN
100 00000064 ea000002 b RRet
101 00000068 RdFLAG
102 00000068 ee150e11 mrc p14, 0, r0, c5, c1, 0 ; Read FLAG
103 0000006c ea000000 b RRet
104 00000070 RdEVTSEL
105 00000070 ee180e11 mrc p14, 0, r0, c8, c1, 0 ; Read EVTSEL
106 00000074
107 00000074 RRet
108 00000074 IF :DEF: Interworking
109 00000074 IF Interworking :LOR: Thumbing
110 00000074 e12fff1e bx lr
111 00000078 ELSE
113 00000078 ENDIF
114 00000078 ELSE
116 00000078 ENDIF
117 00000078
118 00000078 ENDFUNC
119 00000078
120 00000078 ;
121 00000078 ; XllpWritePMUReg - Writes to the PMU Register
122 00000078 ;
123 00000078 ; Description:
124 00000078 ; This routine writes to the designated PMU register via CoProcesser 14.
125 00000078 ;
126 00000078 ; Input Parameters:
127 00000078 ; r0 - arg1 - PMU register number to write
128 00000078 ; r1 - arg2 - Value to write to PMU register
129 00000078 ;
130 00000078 ; if r0 contains:
131 00000078 ; 0 -> PMNC, PMU Control Register
132 00000078 ; 1 -> CCNT, PMU Clock Counter
133 00000078 ; 2 -> PMN0, PMU Count Register 0
134 00000078 ; 3 -> PMN1, PMU Count Register 1
135 00000078 ; 4 -> PMN2, PMU Count Register 2
136 00000078 ; 5 -> PMN3, PMU Count Register 3
137 00000078 ; 6 -> INTEN, PMU Interupt Enable Register
138 00000078 ; 7 -> FLAG, PMU Overflow Flag Status Register
139 00000078 ; 8 -> EVTSEL PMU Event Select Register
140 00000078 ;
141 00000078 ; Returns:
142 00000078 ; None
143 00000078 ;
144 00000078 ; Registers Modified:
145 00000078 ; CoProcessor Register Modified: PMU Register
146 00000078 ; General Purpose Registers Modified: None
147 00000078 ;
148 00000078 ; NOTE
149 00000078 ; Error checking not included
150 00000078 ;
151 00000078
152 00000078 XllpWritePMUReg FUNCTION
153 00000078
154 00000078 e3500008 cmp r0, #8
155 0000007c 908ff100 addls pc, pc, r0, lsl #2
156 00000080 ea000019 b WRet
157 00000084 ea000007 b WrPMNC
158 00000088 ea000008 b WrCCNT
159 0000008c ea000009 b WrPMN0
160 00000090 ea00000a b WrPMN1
161 00000094 ea00000b b WrPMN2
162 00000098 ea00000c b WrPMN3
163 0000009c ea00000d b WrINTEN
164 000000a0 ea00000e b WrFLAG
165 000000a4 ea00000f b WrEVTSEL
166 000000a8
167 000000a8 WrPMNC
168 000000a8 ee001e11 mcr p14, 0, r1, c0, c1, 0 ; Write PMNC
169 000000ac ea00000e b WRet
170 000000b0 WrCCNT
171 000000b0 ee011e11 mcr p14, 0, r1, c1, c1, 0 ; Write CCNT
172 000000b4 ea00000c b WRet
173 000000b8 WrPMN0
174 000000b8 ee001e12 mcr p14, 0, r1, c0, c2, 0 ; Write PMN0
175 000000bc ea00000a b WRet
176 000000c0 WrPMN1
177 000000c0 ee011e12 mcr p14, 0, r1, c1, c2, 0 ; Write PMN1
178 000000c4 ea000008 b WRet
179 000000c8 WrPMN2
180 000000c8 ee021e12 mcr p14, 0, r1, c2, c2, 0 ; Write PMN2
181 000000cc ea000006 b WRet
182 000000d0 WrPMN3
183 000000d0 ee031e12 mcr p14, 0, r1, c3, c2, 0 ; Write PMN3
184 000000d4 ea000004 b WRet
185 000000d8 WrINTEN
186 000000d8 ee041e11 mcr p14, 0, r1, c4, c1, 0 ; Write INTEN
187 000000dc ea000002 b WRet
188 000000e0 WrFLAG
189 000000e0 ee051e11 mcr p14, 0, r1, c5, c1, 0 ; Write FLAG
190 000000e4 ea000000 b WRet
191 000000e8 WrEVTSEL
192 000000e8 ee081e11 mcr p14, 0, r1, c8, c1, 0 ; Write EVTSEL
193 000000ec
194 000000ec WRet
195 000000ec IF :DEF: Interworking
196 000000ec IF Interworking :LOR: Thumbing
197 000000ec e12fff1e bx lr
198 000000f0 ELSE
200 000000f0 ENDIF
201 000000f0 ELSE
203 000000f0 ENDIF
204 000000f0
205 000000f0
206 000000f0
207 000000f0 ENDFUNC
208 000000f0
209 000000f0 END
Assembly terminated, errors: 0, warnings: 0
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