📄 xllp_cpdvm.lst
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185 00000000 xlli_MDREFR_SLFRSH EQU (0x00400000) ; Self Refresh Control Status bit
186 00000000 xlli_MDREFR_APD EQU (0x00100000) ; Auto Power Down bit
187 00000000 xlli_MDREFR_K2DB2 EQU (0x00080000) ; SDRAM clock pin 2 divide by 2 control/status
188 00000000 xlli_MDREFR_K1DB2 EQU (0x00020000) ; SDRAM clock pin 1 divide by 2 control/status
189 00000000 xlli_MDREFR_K1RUN EQU (0x00010000) ; SDRAM clock pin 1 run/control status
190 00000000 xlli_MDREFR_E1PIN EQU (0x00008000) ; SDRAM clock Enable pin 1 level control/status
191 00000000 xlli_MDREFR_K0DB2 EQU (0x00004000) ; Sync Static Memory Clock divide by 2 control/status
192 00000000 xlli_MDREFR_K0RUN EQU (0x00002000) ; Sync Static Memory Clock Pin 0
193 00000000 xlli_MDREFR_E0PIN EQU (0x00000100) ; SDRAM clock enable pin 0 (Cotulla ONLY!!)
194 00000000
195 00000000 xlli_MDCNFG_DE0 EQU (0x00000001) ; SDRAM enable bit for partition 0
196 00000000 xlli_MDCNFG_DE1 EQU (0x00000002) ; SDRAM enable bit for partition 1
197 00000000 xlli_MDCNFG_DE2 EQU (0x00010000) ; SDRAM enable bit for partition 2
198 00000000 xlli_MDCNFG_DE3 EQU (0x00020000) ; SDRAM enable bit for partition 3
199 00000000 xlli_MDCNFG_DWID0 EQU (0x00000004) ; SDRAM bus width (clear = 32 bits, set = 16 bits)
200 00000000
201 00000000 ;
202 00000000 ; INTERNAL MEMORY CONTROLLER base address and register offsets from the base address
203 00000000 ;
204 00000000
205 00000000 xlli_IMEMORY_CONFIG_BASE EQU (0x58000000)
206 00000000
207 00000000 xlli_IMPMCR_offset EQU (0x00) ; Internal Memory Power Manager Control Register
208 00000000 xlli_IMPMSR_offset EQU (0x08) ; Internal Memory Power Management Status Register
209 00000000
210 00000000
211 00000000 ;
212 00000000 ; UART Definitions
213 00000000 ;
214 00000000 xlli_perif_base EQU (0x40000000) ; Base address of the peripherals
215 00000000 xlli_ffuart_offset EQU (0x00100000) ; Offset to the Full-Feature UART in the peripheral block
216 00000000 xlli_btuart_offset EQU (0x00200000) ; Offset to the BlueTooth UART in the peripheral block
217 00000000 xlli_stuart_offset EQU (0x00700000) ; Offset to the Standard UART in the peripheral block
218 00000000
219 00000000
220 00000000 xlli_uart_thr_offset EQU (0x0) ;DLAB = 0 WO 8bit - Transmit Holding Register
221 00000000 xlli_uart_rbr_offset EQU (0x0) ;DLAB = 0 RO 8bit - Recieve Buffer Register
222 00000000 xlli_uart_dll_offset EQU (0x0) ;DLAB = 1 RW 8bit - Divisor Latch Low Register
223 00000000 xlli_uart_ier_offset EQU (0x4) ;DLAB = 0 RW 8bit - Interrupt Enable Register
224 00000000 xlli_uart_dlh_offset EQU (0x4) ;DLAB = 1 RW 8bit - Divisor Latch High Register
225 00000000 xlli_uart_iir_offset EQU (0x8) ;DLAB = X RO 8bit - Interrupt Identification Register
226 00000000 xlli_uart_fcr_offset EQU (0x8) ;DLAB = X WO 8bit - FIFO Control Register
227 00000000 xlli_uart_lcr_offset EQU (0xC) ;DLAB = X RW 8bit - Line Control Register
228 00000000 xlli_uart_mcr_offset EQU (0x10) ;DLAB = X RW 8bit - Modem Control Regiser
229 00000000 xlli_uart_lsr_offset EQU (0x14) ;DLAB = X RO 8bit - Line Status Register
230 00000000 xlli_uart_msr_offset EQU (0x18) ;DLAB = X RO 8bit - Modem Status Register
231 00000000 xlli_uart_spr_offset EQU (0x1C) ;DLAB = X RW 8bit - Scratchpad Register
232 00000000 xlli_uart_isr_offset EQU (0x20) ;DLAB = X RW 8bit - Slow Infrared Select Register
233 00000000 xlli_uart_for_offset EQU (0x24) ;DLAB = X RO FIFO Occupancy Register
234 00000000 xlli_uart_abr_offset EQU (0x28) ;DLAB = X RW Autobaud Control Register
235 00000000 xlli_uart_acr_offset EQU (0x2C) ;DLAB = X Autobaud Count Register
236 00000000
237 00000000 ;
238 00000000 ; INTERRUPT CONTROLLER base address and register offsets from the base address
239 00000000 ;
240 00000000
241 00000000 xlli_INTERREGS_PHYSICAL_BASE EQU (0x40D00000)
242 00000000
243 00000000 xlli_ICIP_offset EQU (0x00) ; Interrupt Controller IRQ Pending Register
244 00000000 xlli_ICMR_offset EQU (0x04) ; Interrupt Controller Mask Register
245 00000000 xlli_ICLR_offset EQU (0x08) ; Interrupt Controller Level Register
246 00000000 xlli_ICFP_offset EQU (0x0C) ; Interrupt Controller FIQ pending Register
247 00000000 xlli_ICPR_offset EQU (0x10) ; Interrupt Controller Pending Register
248 00000000 xlli_ICCR_offset EQU (0x14) ; Interrupt Controller Control Register
249 00000000 xlli_ICHP_offset EQU (0x18) ; Interrupt Controller Highest Priority Reg
250 00000000 xlli_ICMR2_offset EQU (0xA0) ; Interrupt Controller Mask Register 2
251 00000000 xlli_ICLR2_offset EQU (0xA4) ; Interrupt Controller Level Register 2
252 00000000 xlli_ICCR2_offset EQU (0xAC) ; Interrupt Controller Control Register 2
253 00000000
254 00000000 ;
255 00000000 ; CLOCK REGISTERS base address and register offsets from the base address
256 00000000 ;
257 00000000
258 00000000 xlli_CLKREGS_PHYSICAL_BASE EQU (0x41300000)
259 00000000
260 00000000 xlli_CCCR_offset EQU (0x00) ; Core Clock Configuration Register
261 00000000 xlli_CKEN_offset EQU (0x04) ; Clock-Enable Register
262 00000000 xlli_OSCC_offset EQU (0x08) ; Oscillator Configuration Register
263 00000000 xlli_CCSR_offset EQU (0x0C) ; Core Clock Status Register
264 00000000
265 00000000 xlli_CCCR_A_Bit_Mask EQU (0x1 << 25) ; "A" bit is bit 25 in CCCR
266 00000000 ;
267 00000000 ; OS TIMER REGISTERS base address and register offsets from the base address
268 00000000 ;
269 00000000
270 00000000 xlli_OSTREGS_PHYSICAL_BASE EQU (0x40A00000)
271 00000000
272 00000000 xlli_OSMR0_offset EQU (0x00) ; OS Timer Match Register 0
273 00000000 xlli_OSMR1_offset EQU (0x04) ; OS Timer Match Register 1
274 00000000 xlli_OSMR2_offset EQU (0x08) ; OS Timer Match Register 2
275 00000000 xlli_OSMR3_offset EQU (0x0C) ; OS Timer Match Register 3
276 00000000
277 00000000 xlli_OSCR0_offset EQU (0x10) ; OS Timer Count Register 0
278 00000000 xlli_OSSR_offset EQU (0x14) ; OS Timer Status Register
279 00000000 xlli_OWER_offset EQU (0x18) ; OS Timer Watchdog Enable Register
280 00000000 xlli_OIER_offset EQU (0x1C) ; OS Timer Interrupt Enable Register
281 00000000
282 00000000 xlli_OSCR4_offset EQU (0x40) ; OS Timer Count Register 4
283 00000000 xlli_OSCR5_offset EQU (0x44) ; OS Timer Count Register 5
284 00000000 xlli_OSCR6_offset EQU (0x48) ; OS Timer Count Register 6
285 00000000 xlli_OSCR7_offset EQU (0x4C) ; OS Timer Count Register 7
286 00000000 xlli_OSCR8_offset EQU (0x50) ; OS Timer Count Register 8
287 00000000 xlli_OSCR9_offset EQU (0x54) ; OS Timer Count Register 9
288 00000000 xlli_OSCR10_offset EQU (0x58) ; OS Timer Count Register 10
289 00000000 xlli_OSCR11_offset EQU (0x5C) ; OS Timer Count Register 11
290 00000000
291 00000000 xlli_OSMR4_offset EQU (0x80) ; OS Timer Match Register 4
292 00000000 xlli_OSMR5_offset EQU (0x84) ; OS Timer Match Register 5
293 00000000 xlli_OSMR6_offset EQU (0x88) ; OS Timer Match Register 6
294 00000000 xlli_OSMR7_offset EQU (0x8C) ; OS Timer Match Register 7
295 00000000 xlli_OSMR8_offset EQU (0x90) ; OS Timer Match Register 8
296 00000000 xlli_OSMR9_offset EQU (0x94) ; OS Timer Match Register 9
297 00000000 xlli_OSMR10_offset EQU (0x98) ; OS Timer Match Register 10
298 00000000 xlli_OSMR11_offset EQU (0x9C) ; OS Timer Match Register 11
299 00000000
300 00000000 xlli_OMCR4_offset EQU (0xC0) ; OS Timer Match Control Register 4
301 00000000 xlli_OMCR5_offset EQU (0xC4) ; OS Timer Match Control Register 5
302 00000000 xlli_OMCR6_offset EQU (0xC8) ; OS Timer Match Control Register 6
303 00000000 xlli_OMCR7_offset EQU (0xCC) ; OS Timer Match Control Register 7
304 00000000 xlli_OMCR8_offset EQU (0xD0) ; OS Timer Match Control Register 8
305 00000000 xlli_OMCR9_offset EQU (0xD4) ; OS Timer Match Control Register 9
306 00000000 xlli_OMCR10_offset EQU (0xD8) ; OS Timer Match Control Register 10
307 00000000 xlli_OMCR11_offset EQU (0xDC) ; OS Timer Match Control Register 11
308 00000000
309 00000000 xlli_OSSR_ALL EQU (0xFFF) ; Match register status "sticky bits"
310 00000000 xlli_OIER_E1 EQU (0x002) ; Interrupt enable bit for match register #1
311 00000000
312 00000000 ;
313 00000000 ; REAL TIME CLOCK (RTC) REGISTERS base address and register offsets from the base address
314 00000000 ;
315 00000000
316 00000000 xlli_RTCREGS_PHYSICAL_BASE EQU (0x40900000)
317 00000000
318 00000000 xlli_RCNR_offset EQU (0x00) ; RTC Counter Register
319 00000000 xlli_RTAR_offset EQU (0x04) ; RTC Alarm Register
320 00000000 xlli_RTSR_offset EQU (0x08) ; RTC Status Register
321 00000000 xlli_RTTR_offset EQU (0x0C) ; RTC Timer Trim Register
322 00000000 xlli_RDCR_offset EQU (0x10) ; RTC Day Counter Register
323 00000000 xlli_RYCR_offset EQU (0x14) ; RTC Year Counter Register
324 00000000 xlli_RDAR1_offset EQU (0x18) ; RTC Day Alarm Register 1
325 00000000 xlli_RYAR1_offset EQU (0x1C) ; RTC Year Alarm Register 2
326 00000000 xlli_RDAR2_offset EQU (0x20) ; RTC Day Alarm Register 2
327 00000000 xlli_RYAR2_offset EQU (0x24) ; RTC Year Alarm Register 2
328 00000000 xlli_SWCR_offset EQU (0x28) ; Stopwatch Counter Register
329 00000000 xlli_SWAR1_offset EQU (0x2C) ; Stopwatch Alarm Register 1
330 00000000 xlli_SWAR2_offset EQU (0x30) ; Stopwatch Alarm Register 2
331 00000000 xlli_PICR_offset EQU (0x34) ; Periodic Interrupt Counter Register
332 00000000 xlli_PIAR_offset EQU (0x38) ; Periodic Interrupt Alarm Register
333 00000000
334 00000000
335 00000000 ; Oscillator Controller bit defs
336 00000000
337 00000000 xlli_OSCC_OOK EQU (0x01) ; Oscillator OK bit
338 00000000 xlli_OSCC_OON EQU (0x02) ; Timekeeping (32.768KHz) Osc bit
339 00000000 xlli_OSCC_TOUT_EN EQU (0x04) ; Timekeeping Output enable
340 00000000 xlli_OSCC_PIO_EN EQU (0x08) ; Processor Oscillator Output Enable
341 00000000 xlli_OSCC_CRI EQU (0x10) ; Processor Oscillator Output Enable
342 00000000
343 00000000 ;
344 00000000 ; Coprocessor 15 data bits
345 00000000 ;
346 00000000
347 00000000 xlli_control_icache EQU (0x1000) ; bit 12 - i-cache bit
348 00000000 xlli_control_btb EQU (0x0800) ; bit 11 - btb bit
349 00000000 xlli_control_r EQU (0x0200) ; Bit 9
350 00000000 xlli_control_s EQU (0x0100) ; Bit 8
351 00000000 xlli_control_dcache EQU (0x0004) ; Bit 2 - d-cache bit
352 00000000 xlli_control_mmu EQU (0x0001) ; Bit 0 - MMU bit
353 00000000
354 00000000
355 00000000 ;
356 00000000 ; CP 15 related settings
357 00000000 ;
358 00000000
359 00000000 xlli_PID EQU (0x00)
360 00000000 xlli_DACR EQU (0x01)
361 00000000 xlli_CONTROL_DCACHE EQU (0x04)
362 00000000 xlli_CONTROL_MINIDATA_01 EQU (0x10)
363 00000000 xlli_CONTROL_BTB EQU (0x800) ; Brach Target Buffer bit
364 00000000
365 00000000 ;
366 00000000 ; register bit masks - RCSR
367 00000000 ;
368 00000000 xlli_RCSR_HWR EQU (0x01)
369 00000000 xlli_RCSR_WDR EQU (0x02)
370 00000000 xlli_RCSR_SMR EQU (0x04)
371 00000000 xlli_RCSR_GPR EQU (0x08)
372 00000000 xlli_RCSR_ALL EQU (0xF)
373 00000000
374 00000000
375 00000000 ;
376 00000000 ; CPSR Processor constants
377 00000000
378 00000000 xlli_CPSR_Mode_MASK EQU (0x0000001F)
379 00000000 xlli_CPSR_Mode_USR EQU (0x10)
380 00000000 xlli_CPSR_Mode_FIQ EQU (0x11)
381 00000000 xlli_CPSR_Mode_IRQ EQU (0x12)
382 00000000 xlli_CPSR_Mode_SVC EQU (0x13)
383 00000000 xlli_CPSR_Mode_ABT EQU (0x17)
384 00000000 xlli_CPSR_Mode_UND EQU (0x1B)
385 00000000 xlli_CPSR_Mode_SYS EQU (0x1F)
386 00000000
387 00000000 xlli_CPSR_I_Bit EQU (0x80)
388 00000000 xlli_CPSR_F_Bit EQU (0x40)
389 00000000
390 00000000
391 00000000 xlli_PWRMODE_SLEEP EQU (0x00000003) ; Value for cp14: Reg7 to induce sleep.
392 00000000 ; Bit settings
393 00000000 ;
394 00000000 xlli_BIT_0 EQU 0x00000001
395 00000000 xlli_BIT_1 EQU 0x00000002
396 00000000 xlli_BIT_2 EQU 0x00000004
397 00000000 xlli_BIT_3 EQU 0x00000008
398 00000000 xlli_BIT_4 EQU 0x00000010
399 00000000 xlli_BIT_5 EQU 0x00000020
400 00000000 xlli_BIT_6 EQU 0x00000040
401 00000000 xlli_BIT_7 EQU 0x00000080
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