📄 xllp_cpdvm.lst
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ARM macroassembler Page:1
1 00000000 ;******************************************************************************
2 00000000 ; INTEL CONFIDENTIAL
3 00000000 ; Copyright 2002-2004 Intel Corporation All Rights Reserved.
4 00000000 ;
5 00000000 ; The source code contained or described herein and all documents
6 00000000 ; related to the source code (Material) are owned by Intel Corporation
7 00000000 ; or its suppliers or licensors. Title to the Material remains with
8 00000000 ; Intel Corporation or its suppliers and licensors. The Material contains
9 00000000 ; trade secrets and proprietary and confidential information of Intel
10 00000000 ; or its suppliers and licensors. The Material is protected by worldwide
11 00000000 ; copyright and trade secret laws and treaty provisions. No part of the
12 00000000 ; Material may be used, copied, reproduced, modified, published, uploaded,
13 00000000 ; posted, transmitted, distributed, or disclosed in any way without Intel's
14 00000000 ; prior express written permission.
15 00000000 ;
16 00000000 ; No license under any patent, copyright, trade secret or other intellectual
17 00000000 ; property right is granted to or conferred upon you by disclosure or
18 00000000 ; delivery of the Materials, either expressly, by implication, inducement,
19 00000000 ; estoppel or otherwise. Any license under such intellectual property rights
20 00000000 ; must be express and approved by Intel in writing.
21 00000000 ;
22 00000000 ;******************************************************************************
23 00000000 ;
24 00000000 ; FILENAME: xllp_cpdvm.s
25 00000000 ;
26 00000000 ; PURPOSE: Provides low Level routines to the access and control the
27 00000000 ; processor operating frequencies, voltage and state.
28 00000000 ;
29 00000000 ; LAST MODIFIED: 6-Oct-2004
30 00000000 ;
31 00000000 ;******************************************************************************
32 00000000 INCLUDE xlli_Bulverde_defs.inc
1 00000000 ;*********************************************************************************
2 00000000 ;
3 00000000 ; COPYRIGHT (c) 2002 - 2004 Intel Corporation
4 00000000 ;
5 00000000 ; The information in this file is furnished for informational use only,
6 00000000 ; is subject to change without notice, and should not be construed as
7 00000000 ; a commitment by Intel Corporation. Intel Corporation assumes no
8 00000000 ; responsibility or liability for any errors or inaccuracies that may appear
9 00000000 ; in this document or any software that may be provided in association with
10 00000000 ; this document.
11 00000000 ;
12 00000000 ;*********************************************************************************
13 00000000 ;
14 00000000 ; FILENAME: xlli_Bulverde_defs.inc (Core processor address definitions for PXA27x)
15 00000000 ;
16 00000000 ; LAST MODIFIED: 5-Oct-2004
17 00000000 ;
18 00000000 ;******************************************************************************
19 00000000 ;
20 00000000 ; Include file for PXA27x Processor based
21 00000000 ; Cross Platform Low Level Initialization (XLLI)
22 00000000 ;
23 00000000 ;******************************************************************************
24 00000000
25 00000000
26 00000000 ;
27 00000000 ; Processor stepping Values
28 00000000 ;
29 00000000 xlli_PXA27x_CP15_A0_Val EQU (0x69054110)
30 00000000 xlli_PXA27x_CP15_A1_Val EQU (0x69054111)
31 00000000 xlli_PXA27x_CP15_B0_Val EQU (0x69054112)
32 00000000 xlli_PXA27x_CP15_B1_Val EQU (0x69054113)
33 00000000 xlli_PXA27x_CP15_C0_Val EQU (0x69054114)
34 00000000 xlli_PXA27x_CP15_C5_Val EQU (0x69054117)
35 00000000
36 00000000
37 00000000 xlli_PXA27x_JTAG_A0_Val EQU (0x09265013)
38 00000000 xlli_PXA27x_JTAG_A1_Val EQU (0x19265013)
39 00000000 xlli_PXA27x_JTAG_B0_Val EQU (0x29265013)
40 00000000 xlli_PXA27x_JTAG_B1_Val EQU (0x39265013)
41 00000000 xlli_PXA27x_JTAG_C0_Val EQU (0x49265013)
42 00000000 xlli_PXA27x_JTAG_C5_Val EQU (0x79265013)
43 00000000
44 00000000 xlli_PXA27x_A0_stepping EQU (0x0)
45 00000000 xlli_PXA27x_A1_stepping EQU (0x1)
46 00000000 xlli_PXA27x_B0_stepping EQU (0x2)
47 00000000 xlli_PXA27x_B1_stepping EQU (0x3)
48 00000000 xlli_PXA27x_C0_stepping EQU (0x4)
49 00000000
50 00000000
51 00000000 ;
52 00000000 ; GENERAL PURPOSE I/O (GPIO) base address and register offsets from the base address
53 00000000 ;
54 00000000
55 00000000 xlli_GPIOREGS_PHYSICAL_BASE EQU 0x40E00000
56 00000000
57 00000000 ; GPIO register offsets from the base address
58 00000000
59 00000000 xlli_GPLR0_offset EQU (0x000) ; GPIO Level registers
60 00000000 xlli_GPLR1_offset EQU (0x004)
61 00000000 xlli_GPLR2_offset EQU (0x008)
62 00000000 xlli_GPLR3_offset EQU (0x100)
63 00000000
64 00000000 xlli_GPDR0_offset EQU (0x00C) ; GPIO Direction registers
65 00000000 xlli_GPDR1_offset EQU (0x010)
66 00000000 xlli_GPDR2_offset EQU (0x014)
67 00000000 xlli_GPDR3_offset EQU (0x10C)
68 00000000
69 00000000 xlli_GPSR0_offset EQU (0x018) ; GPIO Set registers
70 00000000 xlli_GPSR1_offset EQU (0x01C)
71 00000000 xlli_GPSR2_offset EQU (0x020)
72 00000000 xlli_GPSR3_offset EQU (0x118)
73 00000000
74 00000000 xlli_GPCR0_offset EQU (0x024) ; GPIO Clear registers
75 00000000 xlli_GPCR1_offset EQU (0x028)
76 00000000 xlli_GPCR2_offset EQU (0x02C)
77 00000000 xlli_GPCR3_offset EQU (0x124)
78 00000000
79 00000000 xlli_GAFR0_L_offset EQU (0x054) ; GPIO Alternate function registers (Bits 15:0)
80 00000000 xlli_GAFR0_U_offset EQU (0x058) ; Bits 31:16
81 00000000 xlli_GAFR1_L_offset EQU (0x05c) ; Bits 47:32
82 00000000 xlli_GAFR1_U_offset EQU (0x060) ; Bits 63:48
83 00000000 xlli_GAFR2_L_offset EQU (0x064) ; Bits 79:64
84 00000000 xlli_GAFR2_U_offset EQU (0x068) ; Bits 95:80
85 00000000 xlli_GAFR3_L_offset EQU (0x06C) ; Bits 111:96
86 00000000 xlli_GAFR3_U_offset EQU (0x070) ; Bits 127:112
87 00000000
88 00000000 ;
89 00000000 ; POWER MANAGER base address and register offsets from the base address
90 00000000 ;
91 00000000
92 00000000 xlli_PMRCREGS_PHYSICAL_BASE EQU 0x40F00000
93 00000000
94 00000000 xlli_PMCR_offset EQU (0x00) ; Power Manager Control Register
95 00000000 xlli_PSSR_offset EQU (0x04) ; Power Manager Sleep Status Register
96 00000000 xlli_PSPR_offset EQU (0x08) ; Power Manager Scratch Pad Register
97 00000000 xlli_PWER_offset EQU (0x0C) ; Power Manager Wake-up Enable Register
98 00000000 xlli_PRER_offset EQU (0x10) ; Power Manager GPIO Rising-edge Detect Enable Register
99 00000000 xlli_PFER_offset EQU (0x14) ; Power Manager GPIO Falling-edge Detect Enable Register
100 00000000 xlli_PEDR_offset EQU (0x18) ; Power Manager GPIO Edge Detect Status Register
101 00000000 xlli_PCFR_offset EQU (0x1C) ; Power Manager General Configuration Register
102 00000000 xlli_PGSR0_offset EQU (0x20) ; Power Manager GPIO Sleep State Register for GP [31-0]
103 00000000 xlli_PGSR1_offset EQU (0x24) ; Power Manager GPIO Sleep State Register for GP [63-32]
104 00000000 xlli_PGSR2_offset EQU (0x28) ; Power Manager GPIO Sleep State Register for GP [95-64]
105 00000000 xlli_PGSR3_offset EQU (0x2C) ; Power Manager GPIO Sleep State Register for GP [120-96]
106 00000000 xlli_RCSR_offset EQU (0x30) ; Reset Controller Status Register
107 00000000 xlli_PSLR_offset EQU (0x34) ; Power Manager Sleep Mode Config Register
108 00000000 xlli_PSTR_offset EQU (0x38) ; Power Manager Standby Mode Config Register
109 00000000 xlli_PSNR_offset EQU (0x3C) ; Power Manager Sense Moce Config Register
110 00000000 xlli_PVCR_offset EQU (0x40) ; Power Manager Voltage Change Control Register
111 00000000 xlli_PKWR_offset EQU (0x50) ; Power Manager Keyboard Wake-up Enable Register
112 00000000 xlli_PKSR_offset EQU (0x54) ; Power Manager Keyboard Edge-Detect Status Register
113 00000000 xlli_PI2DBR_offset EQU (0x188) ; Power I2C Data Buffer Register
114 00000000 xlli_PI2CR_offset EQU (0x190) ; Power I2C Control Register
115 00000000 xlli_PI2SR_offset EQU (0x198) ; Power I2C Status Register
116 00000000 xlli_PI2SAR_offset EQU (0x1A0) ; Power I2C Slave Address Register
117 00000000
118 00000000 ;
119 00000000 ; POWER MANAGER register bit masks
120 00000000 ;
121 00000000 xlli_PSSR_SSS EQU (0x01) ; Software Sleep Status
122 00000000 xlli_PSSR_BFS EQU (0x02) ; Battery Fault Status
123 00000000 xlli_PSSR_VFS EQU (0x04) ; VCC Fault Status
124 00000000 xlli_PSSR_PH EQU (0x10) ; Peripheral Control Hold
125 00000000 xlli_PSSR_RDH EQU (0x20) ; Read Disable Hold
126 00000000
127 00000000 xlli_PCFR_OPDE EQU (0x01) ; Processor (13MHz) osc power-down enable
128 00000000 xlli_PCFR_FP EQU (0x02) ; Float PCMCIA during sleep modes
129 00000000 xlli_PCFR_FS EQU (0x04) ; Float Static Chip Selects
130 00000000 xlli_PCFR_GPR_EN EQU (0x10) ; GPIO 1 performs GPIO reset
131 00000000 xlli_PCFR_SYSEN_EN EQU (0x20) ; SYS_EN pin
132 00000000 xlli_PCFR_PI2C_EN EQU (0x40) ;
133 00000000 xlli_PCFR_DC_EN EQU (0x80) ; Deep-Sleep Mode
134 00000000 xlli_PCFR_FVC EQU (0x400) ;
135 00000000 xlli_PCFR_L1_EN EQU (0x800) ;
136 00000000 xlli_PCFR_GPROD EQU (0x1000) ;
137 00000000 xlli_PCFR_PO EQU (0x4000) ;
138 00000000 xlli_PCFR_RO EQU (0x8000) ;
139 00000000 xlli_PCFR_USEDBITS EQU (xlli_PCFR_OPDE :OR: xlli_PCFR_FP :OR: xlli_PCFR_FS :OR: xlli_PCFR_GPR_EN :OR:
xlli_PCFR_SYSEN_EN :OR: xlli_PCFR_PI2C_EN :OR: xlli_PCFR_DC_EN :OR: xlli_PCFR_FVC :OR:
xlli_PCFR_L1_EN :OR: xlli_PCFR_GPROD :OR: xlli_PCFR_PO :OR: xlli_PCFR_RO)
142 00000000
143 00000000 xlli_PWER_WE0 EQU (0x01) ; Wake-up Enable GPIO pin 0
144 00000000 xlli_PWER_WE1 EQU (0x02) ; Wake-up Enable GPIO pin 1
145 00000000 xlli_PWER_WERTC EQU (0x80000000) ; RTC Standby, Wake-up Enable-
146 00000000
147 00000000 ;
148 00000000 ; MEMORY CONTROLLER base address and register offsets from the base address
149 00000000 ;
150 00000000
151 00000000 xlli_MEMORY_CONFIG_BASE EQU 0x48000000
152 00000000
153 00000000 xlli_MDCNFG_offset EQU (0x00)
154 00000000 xlli_MDREFR_offset EQU (0x04)
155 00000000 xlli_MSC0_offset EQU (0x08)
156 00000000 xlli_MSC1_offset EQU (0x0C)
157 00000000 xlli_MSC2_offset EQU (0x10)
158 00000000 xlli_MECR_offset EQU (0x14)
159 00000000 xlli_SXLCR_offset EQU (0x18)
160 00000000 xlli_SXCNFG_offset EQU (0x1C)
161 00000000 xlli_FLYCNFG_offset EQU (0x20)
162 00000000 xlli_SXMRS_offset EQU (0x24)
163 00000000 xlli_MCMEM0_offset EQU (0x28)
164 00000000 xlli_MCMEM1_offset EQU (0x2C)
165 00000000 xlli_MCATT0_offset EQU (0x30)
166 00000000 xlli_MCATT1_offset EQU (0x34)
167 00000000 xlli_MCIO0_offset EQU (0x38)
168 00000000 xlli_MCIO1_offset EQU (0x3C)
169 00000000 xlli_MDMRS_offset EQU (0x40)
170 00000000 xlli_BOOT_DEF_offset EQU (0x44)
171 00000000 xlli_ARB_CNTL_offset EQU (0x48)
172 00000000 xlli_BSCNTR0_offset EQU (0x4C)
173 00000000 xlli_BSCNTR1_offset EQU (0x50)
174 00000000 xlli_LCDBSCNTR_offset EQU (0x54)
175 00000000 xlli_MDMRSLP_offset EQU (0x58)
176 00000000 xlli_BSCNTR2_offset EQU (0x5C)
177 00000000 xlli_BSCNTR3_offset EQU (0x60)
178 00000000
179 00000000 ; Memory Controller bit defs
180 00000000
181 00000000 xlli_MDREFR_K0DB4 EQU (0x20000000) ; Sync Static Clock 0 divide by 4 control/status
182 00000000 xlli_MDREFR_K2FREE EQU (0x02000000) ; Set to force SDCLK[2] to be free running
183 00000000 xlli_MDREFR_K1FREE EQU (0x01000000) ; Set to force SDCLK[1] to be free running
184 00000000 xlli_MDREFR_K0FREE EQU (0x00800000) ; Set to force SDCLK[0] to be free running
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