📄 xllp_usbohci.cod
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; Listing generated by Microsoft (R) Optimizing Compiler Version 13.10.4345
TTL F:\wm520\PLATFORM\intel_dbpxa27x\Public\CSP\ARM\INTEL\PXA27X\XLLP\SOURCE\.\xllp_usbohci.c
CODE32
00000 AREA |.drectve|, DRECTVE
DCB "-defaultlib:coredll.lib "
DCB "-defaultlib:corelibc.lib "
EXPORT |XllpUsbhTurnOnUSBHostClock|
; File f:\wm520\platform\intel_dbpxa27x\public\csp\arm\intel\pxa27x\xllp\inc\xllp_usbohci.h
00000 AREA |.text| { |XllpUsbhTurnOnUSBHostClock| }, CODE, ARM, SELECTION=2 ; comdat any
00000 AREA |.pdata$$XllpUsbhTurnOnUSBHostClock|, PDATA, SELECTION=5, ASSOC=|.text| { |XllpUsbhTurnOnUSBHostClock| } ; comdat associative
|$T978| DCD |$L977|
DCD 0x40000600
; Function compile flags: /Ogsy
00000 AREA |.text| { |XllpUsbhTurnOnUSBHostClock| }, CODE, ARM, SELECTION=2 ; comdat any
00000 |XllpUsbhTurnOnUSBHostClock| PROC
; 386 : {
00000 |$L977|
00000 |$M975|
; 387 : // The clock enable bit for the USB Host OHCI block in PXA27x
; 388 : // is bit 10.
; 389 :
; 390 : pUsbhHandle->pCLKMGRRegs->cken |= XLLP_CLKEN_USBHOST;
00000 e590200c ldr r2, [r0, #0xC]
; 391 :
; 392 : return (XLLP_USBH_SUCCESS);
00004 e3a00000 mov r0, #0
00008 e5923004 ldr r3, [r2, #4]
0000c e3833b01 orr r3, r3, #1, 22
00010 e5823004 str r3, [r2, #4]
; 393 : }
00014 e12fff1e bx lr
00018 |$M976|
ENDP ; |XllpUsbhTurnOnUSBHostClock|
EXPORT |XllpUsbhReset|
IMPORT |XllpOstDelayMicroSeconds|
IMPORT |XllpUsbhConfigPlatformSpecificUSBHReset|
; File f:\wm520\platform\intel_dbpxa27x\public\csp\arm\intel\pxa27x\xllp\source\xllp_usbohci.c
00000 AREA |.text| { |XllpUsbhReset| }, CODE, ARM, SELECTION=1 ; comdat noduplicate
00000 AREA |.pdata$$XllpUsbhReset|, PDATA, SELECTION=5, ASSOC=|.text| { |XllpUsbhReset| } ; comdat associative
|$T989| DCD |$L988|
DCD 0x40001a01
; Function compile flags: /Ogsy
00000 AREA |.text| { |XllpUsbhReset| }, CODE, ARM, SELECTION=1 ; comdat noduplicate
00000 |XllpUsbhReset| PROC
; 52 : {
00000 |$L988|
00000 e92d4010 stmdb sp!, {r4, lr}
00004 |$M986|
00004 e1a04000 mov r4, r0
; 53 : // Do the reset for the Bulverde part.
; 54 : // Two levels of reset need to be initiated:
; 55 : // The OHCI core needs to be reset via the FHR bit,
; 56 : // then the OHCI system bus interface needs to be reset via the FSBIR bit.
; 57 :
; 58 : // Reset the OHC core and all OHC blocks driven by the 12 MHz clock, eg. write fifo, etc.
; 59 : pUsbhHandle->pUSBHRegs->UHCHR |= XLLP_USBOHCI_UHCHR_FHR;
00008 e5942000 ldr r2, [r4]
; 60 :
; 61 : // Wait for ten micro seconds called for by spec.
; 62 : XllpOstDelayMicroSeconds(pUsbhHandle->pOSTRegs, 10) ;
0000c e3a0100a mov r1, #0xA
00010 e5923064 ldr r3, [r2, #0x64]
00014 e3833002 orr r3, r3, #2
00018 e5823064 str r3, [r2, #0x64]
0001c e5940010 ldr r0, [r4, #0x10]
00020 eb000000 bl XllpOstDelayMicroSeconds
; 63 :
; 64 : //Clear FHR bit to enable normal USBH functioning.
; 65 : pUsbhHandle->pUSBHRegs->UHCHR &= ~XLLP_USBOHCI_UHCHR_FHR;
00024 e5942000 ldr r2, [r4]
00028 e5923064 ldr r3, [r2, #0x64]
0002c e3c33002 bic r3, r3, #2
00030 e5823064 str r3, [r2, #0x64]
; 66 :
; 67 : // reset the OHC system bus interface, eg. SBI, DMA blocks, fifos, etc.
; 68 : pUsbhHandle->pUSBHRegs->UHCHR |= XLLP_USBOHCI_UHCHR_FSBIR;
00034 e5942000 ldr r2, [r4]
00038 e5923064 ldr r3, [r2, #0x64]
0003c e3833001 orr r3, r3, #1
00040 e5823064 str r3, [r2, #0x64]
00044 e5942000 ldr r2, [r4]
00048 |$L891|
; 69 :
; 70 : // auto clears in 3 system bus clocks
; 71 : while( pUsbhHandle->pUSBHRegs->UHCHR & XLLP_USBOHCI_UHCHR_FSBIR )
00048 e5923064 ldr r3, [r2, #0x64]
0004c e3130001 tst r3, #1
00050 1afffffc bne |$L891|
; 72 : ;
; 73 :
; 74 : //Init Platform Specific Configuration for USBH Reset
; 75 : //XllpUsbhInitPlatformSpecificConfig(pUsbhHandle);
; 76 :
; 77 : //Call for Platform Specific Configuration for USBH Reset
; 78 : XllpUsbhConfigPlatformSpecificUSBHReset(pUsbhHandle);
00054 e1a00004 mov r0, r4
00058 eb000000 bl XllpUsbhConfigPlatformSpecificUSBHReset
; 79 :
; 80 : return (XLLP_USBH_SUCCESS);
0005c e3a00000 mov r0, #0
; 81 : }
00060 e8bd4010 ldmia sp!, {r4, lr}
00064 e12fff1e bx lr
00068 |$M987|
ENDP ; |XllpUsbhReset|
EXPORT |XllpUsbhSelectPowerManagementMode|
00000 AREA |.text| { |XllpUsbhSelectPowerManagementMode| }, CODE, ARM, SELECTION=1 ; comdat noduplicate
00000 AREA |.pdata$$XllpUsbhSelectPowerManagementMode|, PDATA, SELECTION=5, ASSOC=|.text| { |XllpUsbhSelectPowerManagementMode| } ; comdat associative
|$T1010| DCD |$L1009|
DCD 0x40004901
; Function compile flags: /Ogsy
00000 AREA |.text| { |XllpUsbhSelectPowerManagementMode| }, CODE, ARM, SELECTION=1 ; comdat noduplicate
00000 |XllpUsbhSelectPowerManagementMode| PROC
; 117 : {
00000 |$L1009|
00000 e92d40f0 stmdb sp!, {r4 - r7, lr}
00004 |$M1007|
00004 e1a05003 mov r5, r3
00008 e1a06002 mov r6, r2
0000c e3510000 cmp r1, #0
; 118 : switch(PowerMode)
00010 0a00003c beq |$L906|
00014 e3510001 cmp r1, #1
00018 0a000032 beq |$L907|
0001c e3510002 cmp r1, #2
00020 0a00001b beq |$L908|
00024 e3510003 cmp r1, #3
00028 1a00003a bne |$L903|
; 152 :
; 153 : case XLLP_USBOHCI_PPM_MIXED:
; 154 : // make sure the NO Power Switching mode bit is OFF so Power Switching can occur
; 155 : // make sure the PSM bit is SET, which allows all ports to be controlled with
; 156 : // the PER PORT set and clear power commands
; 157 : pUsbhHandle->pUSBHRegs->UHCRHDA &= ~XLLP_USBOHCI_UHCRHDA_NPS;
0002c e590e000 ldr lr, [r0]
; 158 : pUsbhHandle->pUSBHRegs->UHCRHDA |= XLLP_USBOHCI_UHCRHDA_PSM;
; 159 :
; 160 : // set the power management mode for each individual port to Per Port.
; 161 : // if the value in the pPortMode array is non-zero, set Per Port mode for the port.
; 162 : // if the value in the pPortMode array is zero, set Global mode for the port
; 163 : {
; 164 : XLLP_UINT32_T p;
; 165 :
; 166 : for( p = 0; p < NumPorts; p++ )
00030 e3a04000 mov r4, #0
00034 e3560000 cmp r6, #0
00038 e59e1048 ldr r1, [lr, #0x48]
0003c e3c11c02 bic r1, r1, #2, 24
00040 e58e1048 str r1, [lr, #0x48]
00044 e5901000 ldr r1, [r0]
00048 e5913048 ldr r3, [r1, #0x48]
0004c e3833c01 orr r3, r3, #1, 24
00050 e5813048 str r3, [r1, #0x48]
00054 0a00002f beq |$L903|
00058 e3a0e001 mov lr, #1
0005c e3a07001 mov r7, #1
00060 |$L916|
; 167 : {
; 168 : if( pPortMode[p] )
00060 e5953000 ldr r3, [r5]
; 169 : {
; 170 : pUsbhHandle->pUSBHRegs->UHCRHDB |= (unsigned int)( 1u << (p+17) ); // port 1 begins at bit 17
00064 e5901000 ldr r1, [r0]
00068 e2842011 add r2, r4, #0x11
0006c e3530000 cmp r3, #0
00070 e591304c ldr r3, [r1, #0x4C]
; 171 : }
; 172 : else
; 173 : {
; 174 : pUsbhHandle->pUSBHRegs->UHCRHDB &= ~(unsigned int)( 1u << (p+17) ); // port 1 begins at bit 17
00074 e2844001 add r4, r4, #1
00078 e2855004 add r5, r5, #4
0007c 1183321e orrne r3, r3, lr, lsl r2
00080 01c33217 biceq r3, r3, r7, lsl r2
00084 e1540006 cmp r4, r6
00088 e581304c str r3, [r1, #0x4C]
0008c 3afffff3 bcc |$L916|
; 175 : }
; 176 :
; 177 : }
; 178 : }
; 179 :
; 180 : break;
00090 ea000020 b |$L903|
00094 |$L908|
; 133 :
; 134 : case XLLP_USBOHCI_PPM_PERPORT:
; 135 : // make sure the NO Power Switching mode bit is OFF so Power Switching can occur
; 136 : // make sure the PSM bit is SET, which allows all ports to be controlled with
; 137 : // the PER PORT set and clear power commands
; 138 : pUsbhHandle->pUSBHRegs->UHCRHDA &= ~XLLP_USBOHCI_UHCRHDA_NPS;
00094 e5902000 ldr r2, [r0]
; 139 : pUsbhHandle->pUSBHRegs->UHCRHDA |= XLLP_USBOHCI_UHCRHDA_PSM;
; 140 :
; 141 : // set the power management mode for each individual port to Per Port.
; 142 : {
; 143 : XLLP_UINT32_T p;
; 144 :
; 145 : for( p = 0; p < NumPorts; p++ )
00098 e3a0e000 mov lr, #0
0009c e3560000 cmp r6, #0
000a0 e5923048 ldr r3, [r2, #0x48]
000a4 e3c33c02 bic r3, r3, #2, 24
000a8 e5823048 str r3, [r2, #0x48]
000ac e5902000 ldr r2, [r0]
000b0 e5923048 ldr r3, [r2, #0x48]
000b4 e3833c01 orr r3, r3, #1, 24
000b8 e5823048 str r3, [r2, #0x48]
000bc 0a000015 beq |$L903|
000c0 e3a04001 mov r4, #1
000c4 |$L910|
; 146 : {
; 147 : pUsbhHandle->pUSBHRegs->UHCRHDB |= (unsigned int)( 1u << (p+17) ); // port 1 begins at bit 17
000c4 e5901000 ldr r1, [r0]
000c8 e28e2011 add r2, lr, #0x11
000cc e28ee001 add lr, lr, #1
000d0 e591304c ldr r3, [r1, #0x4C]
000d4 e15e0006 cmp lr, r6
000d8 e1833214 orr r3, r3, r4, lsl r2
000dc e581304c str r3, [r1, #0x4C]
000e0 3afffff7 bcc |$L910|
; 148 : }
; 149 : }
; 150 :
; 151 : break;
000e4 ea00000b b |$L903|
000e8 |$L907|
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