📄 xlli_lowlev_init.lst
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404 00000000 xlli_DRI_169 EQU (0x028) ; 169 MHz setting
405 00000000 xlli_DRI_175 EQU (0x029)
406 00000000 xlli_DRI_182 EQU (0x02B)
407 00000000 xlli_DRI_188 EQU (0x02D)
408 00000000 xlli_DRI_195 EQU (0x02E)
409 00000000 xlli_DRI_201 EQU (0x030)
410 00000000 xlli_DRI_208 EQU (0x031) ; 208 MHz setting
411 00000000
412 00000000 ENDIF ; xlli_SDRAM_WIDTH_16_BIT
413 00000000
414 00000000 ;
415 00000000 ; SDRAM Settings
416 00000000 ;
417 00000000 IF :DEF: xlli_SDRAM_WIDTH_16_BIT
419 00000000 ELSE
420 00000000 xlli_MDCNFG_value EQU (0x00000AC8) ; SDRAM Config Reg (Non-MCP Version)
421 00000000 ENDIF
422 00000000
423 00000000 xlli_MDMRS_value EQU (0x00000000) ; SDRAM Mode Reg Set Config Reg
424 00000000
425 00000000 ;
426 00000000 ; MEMORY PHYSICAL BASE ADDRESS(S)
427 00000000 ;
428 00000000
429 00000000 xlli_SRAM_PHYSICAL_BASE EQU (0X5C000000) ; Physical base address for SRAM
430 00000000 xlli_SDRAM_PHYSICAL_BASE EQU (0xA0000000) ; Physical base address for SDRAM
431 00000000
432 00000000 ;
433 00000000 ; CORE, SYSTEM BUS, MEMORY BUS Default frequency setting for Mainstone
434 00000000 ;
435 00000000 xlli_CCCR_value EQU (0x00000107) ; PXA27x (HW reset value to start)
436 00000000 ;
437 00000000 ; Clock Enable Register (CKEN) setting
438 00000000 ;
439 00000000 xlli_CKEN_value EQU (0x00400240) ; Data to be set into the clock enable register
440 00000000 ; Bit 6 enables FFUART
441 00000000 ; bit 9 enables OS timers
442 00000000 ; Bit 22 enables memory clock
443 00000000 ;
444 00000000 ; Address where system configuration data is stored
445 00000000 ;
446 00000000 xlli_SCR_data EQU 0x5C03FFFC ; Address of system config data
447 00000000
448 00000000 ;
449 00000000 ; Misc constants
450 00000000 ;
451 00000000 xlli_MemSize_1Mb EQU 0x00100000
452 00000000 IF :DEF: xlli_SDRAM_SIZE_32_MB
454 00000000 ENDIF
455 00000000 IF :DEF: xlli_SDRAM_SIZE_64_MB
456 00000000 xlli_p_PageTable EQU 0xA3FFC000 ; Base address for memory Page Table (Non-MCP version)
457 00000000 ENDIF
458 00000000 IF :DEF: xlli_SDRAM_SIZE_128_MB
460 00000000 ENDIF
461 00000000 xlli_s_PageTable EQU 0x00004000 ; Page Table size (4K words - 16 Kb)
462 00000000
463 00000000
464 00000000 xlli_FLASH_WRITE_CMD EQU 0x0060 ; Code for writing to flash
465 00000000 xlli_FLASH_WCONF_CMD EQU 0x0003 ; Code to confirm write to flash
466 00000000 xlli_FLASH_READ_CMD EQU 0x00FF ; Code to place flash in read mode
467 00000000 xlli_FLASH_READQUERY_CMD EQU 0x0098 ; Code to place flash in a 'query CFI' mode
468 00000000
469 00000000 ;
470 00000000 ; Note 1: For the current L3/L18 flash, it has a maximium frequency of 52MHz. In addition, the SXCNFG.LC value is based on t
he
471 00000000 ; SDClk presented to the flash, not the MEMClk as with most other Memory Controller settings, a bit odd, but so be it
.
472 00000000 ;
473 00000000 ; Note 2: We have just optimized these values for 52MHz SDClk to the Flash part. The OEM could optimize this for other SDClk
values,
474 00000000 ; but as there are so many, and the predominant Intel supported frequencies put the flash part into 52MHz operation,
it
475 00000000 ; made more sense to focus on the code, as each OEM will decide how best to run/optimize their platform.
476 00000000 ;
477 00000000 ; Explaination of RCR value:
478 00000000 ;
479 00000000 ; Read Mode = 0x0 = Sync. Mode
480 00000000 ; Latency Count = 0x5
481 00000000 ; Wait Polarity = 0x0 = Wait active low
482 00000000 ; Data Hold = 0x0 = Hold for 1 clock
483 00000000 ; Wait Delay = 0x1 = Wait de-asserted 1 dcycle before valid data
484 00000000 ; Burst Sequence = 0x1 = Linear
485 00000000 ; Clock Edge = 0x1 = Rising
486 00000000 ; Burst Wrap = 0x0 = wrap
487 00000000 ; Burst length = 0x3 = 16 word burst
488 00000000 ;
489 00000000 ; Note on Burst Length: Spacial locality suggests that having a burst of 16 will give better results than that of 8, ho
wever,
490 00000000 ; be aware that 8 words is a cache line, so it may be more beneficial to revert to a burst length of 8 words per
491 00000000 ; burst as opposed to 16 words per burst
492 00000000 ;
493 00000000 xlli_FLASH_RCR16_value EQU 0x25C3<<1 ; Value to set flash into sync mode - optimal RC.LC value for 52MHz flash is 5
494 00000000 xlli_FLASH_RCR32_value EQU 0x25C3<<2 ; Value to set flash into sync mode - optimal RC.LC value for 52MHz flash is 5
495 00000000
496 00000000 ;
497 00000000 ; Value below is simply to align with the settings put in for the flash RCR value
498 00000000 ;
499 00000000 xlli_SXCNFG_sync_value EQU 0x7011 ; SXCNFG value for sync flash operation - optimal SXCNFG.LC value for 52MHz fl
ash is 4
500 00000000
501 00000000 ;
502 00000000 ; Values to put the flash back into Asynchronous mode
503 00000000 ;
504 00000000 xlli_FLASH_ASYNC_RCR16_value EQU 0xA5C2<<1 ; Value to set flash into sync mode - optimal RC.LC value for 52MHz fl
ash is 5
505 00000000 xlli_FLASH_ASYNC_RCR32_value EQU 0xA5C2<<2 ; Value to set flash into sync mode - optimal RC.LC value for 52MHz fl
ash is 5
506 00000000 xlli_SXCNFG_async_value EQU 0x7010 ; SXCNFG value for sync flash operation - optimal SXCNFG.LC value for
52MHz flash is 4
507 00000000
508 00000000
509 00000000 ;
510 00000000 ; Types of flash that XLLI can discover include:
511 00000000 ;
512 00000000 ; TYPE CODE RANGE
513 00000000 ; ---- ----------------
514 00000000 ; J3 = 0x16 -> 0x18
515 00000000 ; K3 = 0x8801 -> 0x8803
516 00000000 ; K18 = 0x8805 -> 0x8807
517 00000000 ; L18 = 0x880E -> 0x8810
518 00000000 ; L3 = 0x8812 -> 0x8815
519 00000000 ;
520 00000000 xlli_J3_FlashID_Code EQU 0x0018 ; return value of J3 in parallel mode
521 00000000 xlli_K3_FlashID_Code EQU 0x8803 ; use the upper (so can compare as <=
522 00000000 xlli_K18_FlashID_Code EQU 0x8807 ; use the upper (so can compare as <=
523 00000000 xlli_L18_FlashID_Code EQU 0x8810 ; use the upper (so can compare as <=
524 00000000 xlli_L3_FlashID_Code EQU 0x8815 ; use the upper (so can compare as <=
525 00000000
526 00000000
527 00000000 ;
528 00000000 ; Special conditional required for Power On SelfTest (POST) build
529 00000000 ;
530 00000000 IF :DEF: POST_BUILD
532 00000000 ELSE
533 00000000 xlli_v_xbBOOTROM EQU 0x00000000 ; Everything else
534 00000000 ENDIF
535 00000000
536 00000000 END
47 00000000 INCLUDE xlli_LowLev_mac.mac ; Mainstone Macro definitions
1 00000000 ;*********************************************************************************
2 00000000 ;
3 00000000 ; COPYRIGHT (c) 2002 Intel Corporation
4 00000000 ;
5 00000000 ; The information in this file is furnished for informational use only,
6 00000000 ; is subject to change without notice, and should not be construed as
7 00000000 ; a commitment by Intel Corporation. Intel Corporation assumes no
8 00000000 ; responsibility or liability for any errors or inaccuracies that may appear
9 00000000 ; in this document or any software that may be provided in association with
10 00000000 ; this document.
11 00000000 ;
12 00000000 ;*********************************************************************************
13 00000000 ;
14 00000000 ; xlli_LowLev_mac.mac
15 00000000 ; MainStone Platform Low Level Macros
16 00000000 ;
17 00000000 ; Copyright (c) 2002 by Intel Corp. Hudson MA
18 00000000 ;
19 00000000 ; List of macros in this file:
20 00000000 ;
21 00000000 ;
22 00000000 ; xlli_mapSECTIONS (Macro) Generates page table entries for MMU
23 00000000 ;
24 00000000 ;*********************************************************************************
25 00000000
26 00000000
27 00000000
28 00000000
29 00000000 ;*********************************************************************************
30 00000000 ; This macro will map a region using 1MB sections
31 00000000 ; Notes:
32 00000000 ; 1)You must call xlli_initPageTable before this macro is valid.
33 00000000 ; 2) This version of the macro is used when NAMED values are passed to the macro
34 00000000
35 00000000 MACRO
36 00000000 xlli_mapSECTIONS $w1, $w2, $w3, $w4, $size, $virtual, $physical, $access, $Level1tab
37 00000000
38 00000000 ; $size = size of region to be mapped
39 00000000 ; $virtual = starting virtual address of region
40 00000000 ; $physical = starting physical address of region
41 00000000 ; $access = access bits for this region
42 00000000 ; $tabl = physical (base) address of page tables
43 00000000 ; $Level1tab = offset from page table base to level 1 entries
44 00000000
45 00000000 ; get the page table base address from cp15
46 00000000
47 00000000 mrc p15, 0, $w4, c2, c0, 0 ⌨️ 快捷键说明
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