📄 xlli_lowlev_init.lst
字号:
327 00000000 xlli_RYAR2_offset EQU (0x24) ; RTC Year Alarm Register 2
328 00000000 xlli_SWCR_offset EQU (0x28) ; Stopwatch Counter Register
329 00000000 xlli_SWAR1_offset EQU (0x2C) ; Stopwatch Alarm Register 1
330 00000000 xlli_SWAR2_offset EQU (0x30) ; Stopwatch Alarm Register 2
331 00000000 xlli_PICR_offset EQU (0x34) ; Periodic Interrupt Counter Register
332 00000000 xlli_PIAR_offset EQU (0x38) ; Periodic Interrupt Alarm Register
333 00000000
334 00000000
335 00000000 ; Oscillator Controller bit defs
336 00000000
337 00000000 xlli_OSCC_OOK EQU (0x01) ; Oscillator OK bit
338 00000000 xlli_OSCC_OON EQU (0x02) ; Timekeeping (32.768KHz) Osc bit
339 00000000 xlli_OSCC_TOUT_EN EQU (0x04) ; Timekeeping Output enable
340 00000000 xlli_OSCC_PIO_EN EQU (0x08) ; Processor Oscillator Output Enable
341 00000000 xlli_OSCC_CRI EQU (0x10) ; Processor Oscillator Output Enable
342 00000000
343 00000000 ;
344 00000000 ; Coprocessor 15 data bits
345 00000000 ;
346 00000000
347 00000000 xlli_control_icache EQU (0x1000) ; bit 12 - i-cache bit
348 00000000 xlli_control_btb EQU (0x0800) ; bit 11 - btb bit
349 00000000 xlli_control_r EQU (0x0200) ; Bit 9
350 00000000 xlli_control_s EQU (0x0100) ; Bit 8
351 00000000 xlli_control_dcache EQU (0x0004) ; Bit 2 - d-cache bit
352 00000000 xlli_control_mmu EQU (0x0001) ; Bit 0 - MMU bit
353 00000000
354 00000000
355 00000000 ;
356 00000000 ; CP 15 related settings
357 00000000 ;
358 00000000
359 00000000 xlli_PID EQU (0x00)
360 00000000 xlli_DACR EQU (0x01)
361 00000000 xlli_CONTROL_DCACHE EQU (0x04)
362 00000000 xlli_CONTROL_MINIDATA_01 EQU (0x10)
363 00000000 xlli_CONTROL_BTB EQU (0x800) ; Brach Target Buffer bit
364 00000000
365 00000000 ;
366 00000000 ; register bit masks - RCSR
367 00000000 ;
368 00000000 xlli_RCSR_HWR EQU (0x01)
369 00000000 xlli_RCSR_WDR EQU (0x02)
370 00000000 xlli_RCSR_SMR EQU (0x04)
371 00000000 xlli_RCSR_GPR EQU (0x08)
372 00000000 xlli_RCSR_ALL EQU (0xF)
373 00000000
374 00000000
375 00000000 ;
376 00000000 ; CPSR Processor constants
377 00000000
378 00000000 xlli_CPSR_Mode_MASK EQU (0x0000001F)
379 00000000 xlli_CPSR_Mode_USR EQU (0x10)
380 00000000 xlli_CPSR_Mode_FIQ EQU (0x11)
381 00000000 xlli_CPSR_Mode_IRQ EQU (0x12)
382 00000000 xlli_CPSR_Mode_SVC EQU (0x13)
383 00000000 xlli_CPSR_Mode_ABT EQU (0x17)
384 00000000 xlli_CPSR_Mode_UND EQU (0x1B)
385 00000000 xlli_CPSR_Mode_SYS EQU (0x1F)
386 00000000
387 00000000 xlli_CPSR_I_Bit EQU (0x80)
388 00000000 xlli_CPSR_F_Bit EQU (0x40)
389 00000000
390 00000000
391 00000000 xlli_PWRMODE_SLEEP EQU (0x00000003) ; Value for cp14: Reg7 to induce sleep.
392 00000000 ; Bit settings
393 00000000 ;
394 00000000 xlli_BIT_0 EQU 0x00000001
395 00000000 xlli_BIT_1 EQU 0x00000002
396 00000000 xlli_BIT_2 EQU 0x00000004
397 00000000 xlli_BIT_3 EQU 0x00000008
398 00000000 xlli_BIT_4 EQU 0x00000010
399 00000000 xlli_BIT_5 EQU 0x00000020
400 00000000 xlli_BIT_6 EQU 0x00000040
401 00000000 xlli_BIT_7 EQU 0x00000080
402 00000000 xlli_BIT_8 EQU 0x00000100
403 00000000 xlli_BIT_9 EQU 0x00000200
404 00000000 xlli_BIT_10 EQU 0x00000400
405 00000000 xlli_BIT_11 EQU 0x00000800
406 00000000 xlli_BIT_12 EQU 0x00001000
407 00000000 xlli_BIT_13 EQU 0x00002000
408 00000000 xlli_BIT_14 EQU 0x00004000
409 00000000 xlli_BIT_15 EQU 0x00008000
410 00000000 xlli_BIT_16 EQU 0x00010000
411 00000000 xlli_BIT_17 EQU 0x00020000
412 00000000 xlli_BIT_18 EQU 0x00040000
413 00000000 xlli_BIT_19 EQU 0x00080000
414 00000000 xlli_BIT_20 EQU 0x00100000
415 00000000 xlli_BIT_21 EQU 0x00200000
416 00000000 xlli_BIT_22 EQU 0x00400000
417 00000000 xlli_BIT_23 EQU 0x00800000
418 00000000 xlli_BIT_24 EQU 0x01000000
419 00000000 xlli_BIT_25 EQU 0x02000000
420 00000000 xlli_BIT_26 EQU 0x04000000
421 00000000 xlli_BIT_27 EQU 0x08000000
422 00000000 xlli_BIT_28 EQU 0x10000000
423 00000000 xlli_BIT_29 EQU 0x20000000
424 00000000 xlli_BIT_30 EQU 0x40000000
425 00000000 xlli_BIT_31 EQU 0x80000000
426 00000000 END
46 00000000 INCLUDE xlli_Mainstone_defs.inc ; Mainstone specific include file
1 00000000 ;*********************************************************************************
2 00000000 ;
3 00000000 ; COPYRIGHT (c) 2002 - 2004 Intel Corporation
4 00000000 ;
5 00000000 ; The information in this file is furnished for informational use only,
6 00000000 ; is subject to change without notice, and should not be construed as
7 00000000 ; a commitment by Intel Corporation. Intel Corporation assumes no
8 00000000 ; responsibility or liability for any errors or inaccuracies that may appear
9 00000000 ; in this document or any software that may be provided in association with
10 00000000 ; this document.
11 00000000 ;
12 00000000 ;*********************************************************************************
13 00000000 ;
14 00000000 ; FILENAME: xlli_Mainstone_defs.inc (Platform specific addresses and
15 00000000 ; defalut values for Mainstone II platform bring up)
16 00000000 ; NOTE: - This file has a def to configure xlli for MCP and non-MCP processors
17 00000000 ;
18 00000000 ; LAST MODIFIED: 4-Aug-2004
19 00000000 ;
20 00000000 ;******************************************************************************
21 00000000 ;
22 00000000 ;
23 00000000 ; Include file for Mainstone II specific Cross Platform Low Level Initialization (XLLI)
24 00000000 ;
25 00000000 ;
26 00000000 ;******************************************************************************
27 00000000
28 00000000
29 00000000 ;
30 00000000 ; CONFIGURATION OPTIONS
31 00000000 ; Note: As there are multiple configuration options and a limited number of switches, it is
32 00000000 ; necessary to make some things compile time specific. WinCE does not use the SDRAM, FLASH
33 00000000 ; or C0 flags, as they are passed via the build environment, but it does use the UART
34 00000000 ; definition
35 00000000 ;
36 00000000
37 00000000 ;xlli_SDRAM_SIZE_32_MB EQU 0 ; Uncomment for 64 Mb of SDRAM
38 00000000 ;xlli_SDRAM_WIDTH_16_BIT EQU 0 ; Uncomment for 16-bit SDRAM bus
39 00000000 ;xlli_FLASH_WIDTH_16_BIT EQU 0 ; Uncomment for 16-bit FLASH bus
40 00000000 ;xlli_C0_BULVERDE EQU 0 ; Uncomment for PXA27x step C0
41 00000000
42 00000000 ;
43 00000000 ; Uncomment out the UART you want for your platform (ffuart, stuart or btuart), but
44 00000000 ; only choose ONE!
45 00000000 ;
46 00000000 ;xlli_Target_UART EQU (xlli_perif_base + xlli_ffuart_offset) ; Uncomment for the ffuart
47 00000000 ;xlli_Target_UART EQU (xlli_perif_base + xlli_stuart_offset) ; Uncomment for the stuart
48 00000000 xlli_Target_UART EQU (xlli_perif_base + xlli_btuart_offset) ; Uncomment for the btuart
49 00000000
50 00000000
51 00000000 ;
52 00000000 ; PLATFORM REGISTERS base address and register offsets from the base address
53 00000000 ;
54 00000000 xlli_PLATFORM_REGISTERS EQU 0x08000000
55 00000000
56 00000000 xlli_PLATFORM_HEXLED_DATA_offset EQU 0x10 ; Hex LED Data Register
57 00000000 xlli_PLATFORM_LED_CONTROL_offset EQU 0x40 ; LED Control Register
58 00000000 xlli_PLATFORM_SWITCH_offset EQU 0x60 ; General Purpose Switch Register
59 00000000 xlli_PLATFORM_MISC_WRITE1_offset EQU 0x80 ; Misc Write Register 1
60 00000000 xlli_PLATFORM_MISC_WRITE2_offset EQU 0x84 ; Misc Write Register 2
61 00000000 xlli_PLATFORM_MISC_READ1_offset EQU 0x90 ; Misc Read Register 1
62 00000000 xlli_PLATFORM_INTERR_ME_offset EQU 0xC0 ; Platform Interrupt Mask/Enable Register 1
63 00000000 xlli_PLATFORM_INTERR_SC_offset EQU 0xD0 ; Platform Interrupt Set/Clear Register 1
64 00000000 xlli_PLATFORM_PCMCIA0_SC_offset EQU 0xE0 ; PCMCIA Socket 0 Status/Control Register
65 00000000 xlli_PLATFORM_PCMCIA1_SC_offset EQU 0xE4 ; PCMCIA Socket 1 Status/Control Register
66 00000000
67 00000000 ;
68 00000000 ; Platform specific bits
69 00000000 ;
70 00000000 xlli_SYS_RESET EQU 0x01 ; System reset bit
71 00000000
72 00000000 ;
73 00000000 ; platform GPIO pin settings (PXA27x/Mainstone)
74 00000000 ;
75 00000000 xlli_GPSR0_value EQU (0x00008004) ; Set registers
76 00000000 xlli_GPSR1_value EQU (0x00020080)
77 00000000 xlli_GPSR2_value EQU (0x16C14000)
78 00000000 xlli_GPSR3_value EQU (0x0003E000)
79 00000000
80 00000000 xlli_GPCR0_value EQU (0x0) ; Clear registers
81 00000000 xlli_GPCR1_value EQU (0x00000380) ; FFUART related
82 00000000 xlli_GPCR2_value EQU (0x0)
83 00000000 xlli_GPCR3_value EQU (0x0)
84 00000000
85 00000000 xlli_GRER0_value EQU (0x0) ; Rising Edge Detect
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -