xllp_wmmx_regs.lst
来自「pxa270为硬件平台的wince操作系统XLLP驱动源码」· LST 代码 · 共 377 行 · 第 1/2 页
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377 行
192 00000080 ; * *
193 00000080 ; ***************************
194 00000080 ;
195 00000080 ; This function is used to restore the WMMX registers. It checks the flags saved in
196 00000080 ; the beginning of the saved area to see if a restore is necessary. If it is unnecessary
197 00000080 ; the routine dumps out, otherwise it calls the "RestoreAll" function.
198 00000080 ;
199 00000080 ; Uses r0 - pointer to the memory buffer containing the WMMX saved area
200 00000080 ;
201 00000080 ;******************************************************************************
202 00000080 Xllp_Restore_WMMX_Regs FUNCTION
203 00000080
204 00000080 e92d401f stmdb sp!, {r0 - r4, r14} ;stack the registers used, so don't munge anything
205 00000084
206 00000084 e4901004 ldr r1, [r0], #4 ;Load the first 4 bytes containing 'if saving' flag
207 00000088 e3510000 cmp r1, #0
208 0000008c 0a000000 beq Skip_Restore
209 00000090
210 00000090 ;Branch to the 'Restore' Function, R0= pointer to save/restore memory area
211 00000090 eb000022 bl Xllp_Restore_All_WMMX_Regs
212 00000094
213 00000094 Skip_Restore
214 00000094 e8bd401f ldmia sp!, {r0 - r4, r14}
215 00000098
216 00000098 IF Interworking :LOR: Thumbing
217 00000098 e12fff1e bx lr
218 0000009c ELSE
220 0000009c ENDIF ; IF Interworking :LOR: Thumbing
221 0000009c
222 0000009c
223 0000009c ENDFUNC
224 0000009c
225 0000009c
226 0000009c ;******************************************************************************
227 0000009c ;
228 0000009c ; *******************************
229 0000009c ; * *
230 0000009c ; * Xllp_Store_All_WMMX_Regs *
231 0000009c ; * *
232 0000009c ; *******************************
233 0000009c ;
234 0000009c ;
235 0000009c ;
236 0000009c ; Stores all WMMX Registers as listed below
237 0000009c ; Saving:
238 0000009c ; CP0, R0 - 15
239 0000009c ; CP1, R2, R3, R8 - 11
240 0000009c ;
241 0000009c ; NOTE: This routine was written to optimize both the read performance and
242 0000009c ; the register usage. It was designed against the EAS stated instruction
243 0000009c ; latencies for tmrc and tmrrc instructions in hopes of keeping the
244 0000009c ; connection between the coprocessor and core maximized with respect to bandwitdh.
245 0000009c ; As such, the registes are not saved in a completely linear fashion, they are
246 0000009c ; interleaved. As a result, the restore must treat these like a stack and pop
247 0000009c ; off the registers in a similar order.
248 0000009c ;
249 0000009c ;******************************************************************************
250 0000009c Xllp_Store_All_WMMX_Regs FUNCTION
251 0000009c
252 0000009c ;; trick - if addr is not double word aligned, save a word to align it
253 0000009c e1a01000 mov r1,r0
254 000000a0 e2102007 ands r2,r0,#7
255 000000a4 0a000000 beq sskip1
256 000000a8 fca12101 stc2 p1, c2, [r1],#4 ;; this instruction is skipped if word aligned
257 000000ac sskip1
258 000000ac ece10002 stcl p0, c0, [r1],#8
259 000000b0 ece11002 stcl p0, c1, [r1],#8
260 000000b4 ece12002 stcl p0, c2, [r1],#8
261 000000b8 ece13002 stcl p0, c3, [r1],#8
262 000000bc ece14002 stcl p0, c4, [r1],#8
263 000000c0 ece15002 stcl p0, c5, [r1],#8
264 000000c4 ece16002 stcl p0, c6, [r1],#8
265 000000c8 ece17002 stcl p0, c7, [r1],#8
266 000000cc ece18002 stcl p0, c8, [r1],#8
267 000000d0 ece19002 stcl p0, c9, [r1],#8
268 000000d4 ece1a002 stcl p0, c10, [r1],#8
269 000000d8 ece1b002 stcl p0, c11, [r1],#8
270 000000dc ece1c002 stcl p0, c12, [r1],#8
271 000000e0 ece1d002 stcl p0, c13, [r1],#8
272 000000e4 ece1e002 stcl p0, c14, [r1],#8
273 000000e8 ece1f002 stcl p0, c15, [r1],#8
274 000000ec 1a000000 bne sskip2 ;; this instruction depend on condition
275 000000f0 ;; set by ANDs above
276 000000f0 fca12101 stc2 p1, c2, [r1],#4 ;; this instruction is executed if word aligned
277 000000f4 sskip2
278 000000f4 fca13101 stc2 p1, c3, [r1],#4
279 000000f8 fca18101 stc2 p1, c8, [r1],#4
280 000000fc fca19101 stc2 p1, c9, [r1],#4
281 00000100 fca1a101 stc2 p1, c10, [r1],#4
282 00000104 fca1b101 stc2 p1, c11, [r1],#4
283 00000108
284 00000108 ; Now clear the control MUP & CUP bits (Control Update Bits)
285 00000108 ; These are WRITE 1 TO CLEAR!
286 00000108 e3a03003 mov r3, #0x3 ;Set the 2 lowest bits == 1
287 0000010c ee013110 mcr p1, 0, r3, c1, c0, 0 ;Now Clear the CUP & MUP bits
288 00000110
289 00000110 ;CPWAIT r0
290 00000110 ee120f10 MRC P15, 0, r0, C2, C0, 0 ; arbitrary read of CP15
291 00000114 e1a02000 MOV r2, r0 ; wait for it (foward dependency)
292 00000118 e24ff004 SUB PC, PC, #4 ; branch to next instruction
293 0000011c
294 0000011c IF Interworking :LOR: Thumbing
295 0000011c e12fff1e bx lr
296 00000120 ELSE
298 00000120 ENDIF ; IF Interworking :LOR: Thumbing
299 00000120
300 00000120 ENDFUNC
301 00000120
302 00000120 ;******************************************************************************
303 00000120 ;
304 00000120 ; *******************************
305 00000120 ; * *
306 00000120 ; * Xllp_Restore_All_WMMX_Regs *
307 00000120 ; * *
308 00000120 ; *******************************
309 00000120 ;
310 00000120 ;
311 00000120 ;
312 00000120 ; Restores all WMMX Registers saved by the above Store function
313 00000120 ; Restoring:
314 00000120 ; CP0, R0 - 15
315 00000120 ; CP1, R2, R3, R8 - 11
316 00000120 ;
317 00000120 ; NOTE: This routine was written to optimize both the read performance and
318 00000120 ; the register usage. It was designed against the EAS stated instruction
319 00000120 ; latencies for tmcr and tmcrr instructions in hopes of keeping the
320 00000120 ; connection between the coprocessor and core maximized with respect to bandwitdh.
321 00000120 ; As such, the registes are not saved in a completely linear fashion, they are
322 00000120 ; interleaved. Due to the order saved, the restore order is also not sequential.
323 00000120 ;
324 00000120 ;******************************************************************************
325 00000120 Xllp_Restore_All_WMMX_Regs FUNCTION
326 00000120
327 00000120 ;; trick - if addr is not double word aligned, save a word to align it
328 00000120 e1a01000 mov r1,r0
329 00000124 e2102007 ands r2,r0,#7
330 00000128 0a000000 beq rskip1
331 0000012c fcb12101 ldc2 p1, c2, [r1],#4 ;; this instruction is skipped if word aligned
332 00000130 rskip1
333 00000130 ecf10002 ldcl p0, c0, [r1],#8
334 00000134 ecf11002 ldcl p0, c1, [r1],#8
335 00000138 ecf12002 ldcl p0, c2, [r1],#8
336 0000013c ecf13002 ldcl p0, c3, [r1],#8
337 00000140 ecf14002 ldcl p0, c4, [r1],#8
338 00000144 ecf15002 ldcl p0, c5, [r1],#8
339 00000148 ecf16002 ldcl p0, c6, [r1],#8
340 0000014c ecf17002 ldcl p0, c7, [r1],#8
341 00000150 ecf18002 ldcl p0, c8, [r1],#8
342 00000154 ecf19002 ldcl p0, c9, [r1],#8
343 00000158 ecf1a002 ldcl p0, c10, [r1],#8
344 0000015c ecf1b002 ldcl p0, c11, [r1],#8
345 00000160 ecf1c002 ldcl p0, c12, [r1],#8
346 00000164 ecf1d002 ldcl p0, c13, [r1],#8
347 00000168 ecf1e002 ldcl p0, c14, [r1],#8
348 0000016c ecf1f002 ldcl p0, c15, [r1],#8
349 00000170 1a000000 bne rskip2 ;; this instruction depend on condition
350 00000174 ;; set by ANDs above
351 00000174 fcb12101 ldc2 p1, c2, [r1],#4 ;; this instruction is executed if word aligned
352 00000178 rskip2
353 00000178 fcb13101 ldc2 p1, c3, [r1],#4
354 0000017c fcb18101 ldc2 p1, c8, [r1],#4
355 00000180 fcb19101 ldc2 p1, c9, [r1],#4
356 00000184 fcb1a101 ldc2 p1, c10, [r1],#4
357 00000188 fcb1b101 ldc2 p1, c11, [r1],#4
358 0000018c
359 0000018c ; Now clear the control MUP & CUP bits (Control Update Bits)
360 0000018c ; These are WRITE 1 TO CLEAR!
361 0000018c e3a01003 mov r1, #0x3 ;Set the 2 lowest bits == 1
362 00000190 ee011110 mcr p1, 0, r1, c1, c0, 0 ;Now Clear the CUP & MUP bits
363 00000194
364 00000194 ;CPWAIT r2
365 00000194 ee122f10 MRC P15, 0, r2, C2, C0, 0 ; arbitrary read of CP15
366 00000198 e1a02002 MOV r2, r2 ; wait for it (foward dependency)
367 0000019c e24ff004 SUB PC, PC, #4 ; branch to next instruction
368 000001a0
369 000001a0
370 000001a0 IF Interworking :LOR: Thumbing
371 000001a0 e12fff1e bx lr
372 000001a4 ELSE
374 000001a4 ENDIF ; IF Interworking :LOR: Thumbing
375 000001a4
376 000001a4
377 000001a4 ENDFUNC
378 000001a4
379 000001a4
380 000001a4 END
Assembly terminated, errors: 0, warnings: 0
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