xllp_wmmx_regs.lst
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ARM macroassembler Page:1
1 00000000 ;******************************************************************************
2 00000000 ;
3 00000000 ; INTEL CONFIDENTIAL
4 00000000 ; Copyright 2002-2003 Intel Corporation All Rights Reserved.
5 00000000 ;
6 00000000 ; The source code contained or described herein and all documents
7 00000000 ; related to the source code (Material) are owned by Intel Corporation
8 00000000 ; or its suppliers or licensors. Title to the Material remains with
9 00000000 ; Intel Corporation or its suppliers and licensors. The Material contains
10 00000000 ; trade secrets and proprietary and confidential information of Intel
11 00000000 ; or its suppliers and licensors. The Material is protected by worldwide
12 00000000 ; copyright and trade secret laws and treaty provisions. No part of the
13 00000000 ; Material may be used, copied, reproduced, modified, published, uploaded,
14 00000000 ; posted, transmitted, distributed, or disclosed in any way without Intel's
15 00000000 ; prior express written permission.
16 00000000 ;
17 00000000 ; No license under any patent, copyright, trade secret or other intellectual
18 00000000 ; property right is granted to or conferred upon you by disclosure or
19 00000000 ; delivery of the Materials, either expressly, by implication, inducement,
20 00000000 ; estoppel or otherwise. Any license under such intellectual property rights
21 00000000 ; must be express and approved by Intel in writing.
22 00000000 ;
23 00000000 ;
24 00000000 ;*********************************************************************************
25 00000000 ;
26 00000000 ; FILENAME: xllp_WMMX_Regs.s
27 00000000 ;
28 00000000 ; PURPOSE: Provides assembly level code to support thread level
29 00000000 ; context saving and restoration for the
30 00000000 ; Bulverde processor's WMMX registers.
31 00000000 ;
32 00000000 ; LAST MODIFIED: 22-Nov-2004
33 00000000 ; AAG - changed load/store to wldr/wstr equivalent, but used LDC/STC to make
34 00000000 ; code assemble one more tool chains. also change tmcr/tmrc to generic
35 00000000 ; mcr/mrc to allow assembly on more tool chains.
36 00000000 ;
37 00000000 ;******************************************************************************
38 00000000 ;
39 00000000 ; NOTES:
40 00000000 ;
41 00000000 ; None.
42 00000000 ;
43 00000000 ;******************************************************************************
44 00000000
45 AREA |.text|, CODE, READONLY, ALIGN=5 ; Align =5 required for "ALIGN 32" to work
46 00000000 ;
47 00000000 ; List of Low Level Init functions in this source code include:
48 00000000 ;
49 00000000 EXPORT Xllp_Read_CoProc_Access
50 00000000 EXPORT Xllp_Set_CoProc_Access
51 00000000 EXPORT Xllp_Save_WMMX_Regs
52 00000000 EXPORT Xllp_Restore_WMMX_Regs
53 00000000 EXPORT Xllp_Store_All_WMMX_Regs
54 00000000 EXPORT Xllp_Restore_All_WMMX_Regs
55 00000000
56 00000000
57 00000000 ;******************************************************************************
58 00000000 ;
59 00000000 ; ***************************
60 00000000 ; * *
61 00000000 ; * Xllp_Read_CoProc_Access *
62 00000000 ; * *
63 00000000 ; ***************************
64 00000000 ;
65 00000000 ; This routine is used to return the coprocessor access bits located in
66 00000000 ; coprocessor 15, register 15. It returns it to the location specified in
67 00000000 ; r0
68 00000000 ;
69 00000000 ;******************************************************************************
70 00000000 Xllp_Read_CoProc_Access FUNCTION
71 00000000
72 00000000 e92d4007 stmdb sp!, {r0 - r2, r14}
73 00000004
74 00000004 ee1f1f11 mrc p15, 0, r1, c15, c1, 0 ;Get Reg15 of CP15 for Access to CP0
75 00000008
76 00000008 ;CPWAIT r2 ;Now 'stall' so the value can have time to be read
77 00000008 ee122f10 MRC P15, 0, r2, C2, C0, 0 ; arbitrary read of CP15
78 0000000c e1a02002 MOV r2, r2 ; wait for it (foward dependency)
79 00000010 e24ff004 SUB PC, PC, #4 ; branch to next instruction
80 00000014
81 00000014 e5801000 str r1, [r0]
82 00000018 e8bd4007 ldmia sp!, {r0 - r2, r14}
83 0000001c
84 0000001c IF Interworking :LOR: Thumbing
85 0000001c e12fff1e bx lr
86 00000020 ELSE
88 00000020 ENDIF ; IF Interworking :LOR: Thumbing
89 00000020
90 00000020 ENDFUNC
91 00000020
92 00000020
93 00000020 ;******************************************************************************
94 00000020 ;
95 00000020 ; ***************************
96 00000020 ; * *
97 00000020 ; * Xllp_Set_CoProc_Access *
98 00000020 ; * *
99 00000020 ; ***************************
100 00000020 ;
101 00000020 ;
102 00000020 ; This routine enables the access bits to Coprocessors 0 & 1
103 00000020 ;
104 00000020 ; Uses R0, R1. R2
105 00000020 ;
106 00000020 ;******************************************************************************
107 00000020 Xllp_Set_CoProc_Access FUNCTION
108 00000020
109 00000020 e92d4007 stmdb sp!, {r0 - r2, r14}
110 00000024
111 00000024 ee1f0f11 mrc p15, 0, r0, c15, c1, 0 ;Get Reg15 of CP15 for Access to CP0
112 00000028 e3a01003 mov r1, #0x3 ;Load R2 with mask for setting lowest bit
113 0000002c e1802001 orr r2, r0, r1 ;OR current value with 1 to set the lowest bit
114 00000030 ee0f2f11 mcr p15, 0, r2, c15, c1, 0 ;Now set the value back into R15 of CP15
115 00000034
116 00000034 ;CPWAIT r0 ;Now 'stall' so the value can have time to be written
117 00000034 ee120f10 MRC P15, 0, r0, C2, C0, 0 ; arbitrary read of CP15
118 00000038 e1a00000 MOV r0, r0 ; wait for it (foward dependency)
119 0000003c e24ff004 SUB PC, PC, #4 ; branch to next instruction
120 00000040
121 00000040 e8bd4007 ldmia sp!, {r0 - r2, r14}
122 00000044
123 00000044 IF Interworking :LOR: Thumbing
124 00000044 e12fff1e bx lr
125 00000048 ELSE
127 00000048 ENDIF ; IF Interworking :LOR: Thumbing
128 00000048
129 00000048 ENDFUNC
130 00000048
131 00000048
132 00000048 ;******************************************************************************
133 00000048 ;
134 00000048 ; ***************************
135 00000048 ; * *
136 00000048 ; * Xllp_Save_WMMX_Regs *
137 00000048 ; * *
138 00000048 ; ***************************
139 00000048 ;
140 00000048 ;
141 00000048 ; This routine is expected to be the entry point for the "SaveAll". It checks
142 00000048 ; the CUP and MUP bits in the control register to see if we need to save, if it
143 00000048 ; is unnecessary, then we simply dump out of the routine. If it is necessary,
144 00000048 ; it sets a flag at the start of the save area and calls "SaveAll" to save all
145 00000048 ; the WMMX registers.
146 00000048 ;
147 00000048 ; Uses r0, - R0 contains a pointer to the alloced memory buffer of 8 bytes long
148 00000048 ;
149 00000048 ;******************************************************************************
150 00000048 Xllp_Save_WMMX_Regs FUNCTION
151 00000048
152 00000048 e92d401f stmdb sp!, {r0 - r4, r14} ;Store registers so we don't stomp anything (INC LR)
153 0000004c
154 0000004c e1a04000 mov r4, r0 ;Save R0 to R4, so pointer value doesn't get killed by CPWAIT
155 00000050
156 00000050 ee111110 mrc p1, 0, r1, c1, c0, 0 ;Grab the CUP & MUP bits in CP1, Reg1
157 00000054
158 00000054 ;CPWAIT r0 ;Now 'stall' so the value can have time to be written
159 00000054 ee120f10 MRC P15, 0, r0, C2, C0, 0 ; arbitrary read of CP15
160 00000058 e1a00000 MOV r0, r0 ; wait for it (foward dependency)
161 0000005c e24ff004 SUB PC, PC, #4 ; branch to next instruction
162 00000060
163 00000060 e2111003 ands r1, r1, #0x3 ;We only are concerned with the lowest 2 bits
164 00000064
165 00000064 ;if flag == 0 then no change since last save, skip save functionality
166 00000064 0a000003 beq Finish_Save
167 00000068
168 00000068 e3a00001 mov r0, #0x1 ;Set a flag in the memory area indicating we have actually SAVED
169 0000006c e4840004 str r0, [r4], #4 ;Save & increment pointer
170 00000070
171 00000070 ; Now branch to the 'save' function, R0 = pointer to save area
172 00000070 e1a00004 mov r0, r4
173 00000074 eb000008 bl Xllp_Store_All_WMMX_Regs
174 00000078
175 00000078 Finish_Save
176 00000078 e8bd401f ldmia sp!, {r0 - r4, r14} ;Now restore the regsiters we stacked3
177 0000007c
178 0000007c IF Interworking :LOR: Thumbing
179 0000007c e12fff1e bx lr
180 00000080 ELSE
182 00000080 ENDIF ; IF Interworking :LOR: Thumbing
183 00000080
184 00000080
185 00000080 ENDFUNC
186 00000080
187 00000080 ;******************************************************************************
188 00000080 ;
189 00000080 ; ***************************
190 00000080 ; * *
191 00000080 ; * Xllp_Restore_WMMX_Regs *
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