xllp_i2sacodec.cod

pxa270为硬件平台的wince操作系统XLLP驱动源码

; Listing generated by Microsoft (R) Optimizing Compiler Version 13.10.4345 

	TTL	F:\wm520\PLATFORM\intel_dbpxa27x\Public\CSP\ARM\INTEL\PXA27X\XLLP\SOURCE\.\xllp_i2sacodec.c
	CODE32

  00000			 AREA	 |.drectve|, DRECTVE
	DCB	"-defaultlib:coredll.lib "
	DCB	"-defaultlib:corelibc.lib "

	EXPORT	|XllpI2sACodecInit|
	IMPORT	|XllpOstDelayMicroSeconds|
; File f:\wm520\platform\intel_dbpxa27x\public\csp\arm\intel\pxa27x\xllp\source\xllp_i2sacodec.c

  00000			 AREA	 |.text| { |XllpI2sACodecInit| }, CODE, ARM, SELECTION=1 ; comdat noduplicate

  00000			 AREA	 |.pdata$$XllpI2sACodecInit|, PDATA, SELECTION=5, ASSOC=|.text| { |XllpI2sACodecInit| } ; comdat associative
|$T1268| DCD	|$L1267|
	DCD	0x40004601
; Function compile flags: /Ogsy

  00000			 AREA	 |.text| { |XllpI2sACodecInit| }, CODE, ARM, SELECTION=1 ; comdat noduplicate

  00000		 |XllpI2sACodecInit| PROC

; 36   : {

  00000		 |$L1267|
  00000	e92d4010	 stmdb       sp!, {r4, lr}
  00004		 |$M1265|
  00004	e1a04000	 mov         r4, r0

; 37   :     int k= 0;
; 38   : 
; 39   : /* Initialize the I2S bus */
; 40   :  
; 41   :     
; 42   : //  clearing the GPIO's value to write the correct value in
; 43   : 	(pDeviceContext->pGpioReg)->GAFR0_U &= ~( XLLP_GPIO_AF_BIT_I2SBITCLK_IN_MASK | 
; 44   : 					   ( XLLP_GPIO_AF_BIT_I2S_SDATA_IN_MASK)|
; 45   : 	   				   ( XLLP_GPIO_AF_BIT_I2S_SDATA_OUT_MASK)|
; 46   : 	   				   ( XLLP_GPIO_AF_BIT_I2S_SYNC_MASK) );

  00008	e5942004	 ldr         r2, [r4, #4]

; 47   :     
; 48   : 	(pDeviceContext->pGpioReg)->GAFR3_U &=   ~( XLLP_GPIO_AF_BIT_I2S_SYSCLK_MASK );
; 49   :     
; 50   : 	(pDeviceContext->pGpioReg)->GPDR0 |= (XLLP_GPIO_BIT_I2SBITCLK|XLLP_GPIO_BIT_I2S_SDATA_OUT|XLLP_GPIO_BIT_I2S_SYNC);
; 51   :     
; 52   : 	//(pDeviceContext->pGpioReg)->GPDR0 &= ~XLLP_GPIO_BIT_I2S_SDATA_IN;
; 53   : 	(pDeviceContext->pGpioReg)->GPDR3 |= (XLLP_GPIO_BIT_I2S_SYSCLK );
; 54   :     
; 55   : 
; 56   : //  sets the alternate function to make the processor the master and the codec the slave
; 57   : //  and to generate the bit clock output
; 58   : 	(pDeviceContext->pGpioReg)->GAFR0_U |= ( ( XLLP_GPIO_AF_BIT_I2SBITCLK_OUT ) | 
; 59   : 	   				   ( XLLP_GPIO_AF_BIT_I2S_SDATA_OUT )|
; 60   : 	   				   ( XLLP_GPIO_AF_BIT_I2S_SYNC) );  //( XLLP_GPIO_AF_BIT_I2S_SDATA_IN )|
; 61   : 
; 62   : 	(pDeviceContext->pGpioReg)->GAFR3_U |=   ( XLLP_GPIO_AF_BIT_I2S_SYSCLK );
; 63   : 
; 64   :    	
; 65   :     XllpOstDelayMicroSeconds( pDeviceContext->pOSTRegs,100);

  0000c	e3a01064	 mov         r1, #0x64
  00010	e5923058	 ldr         r3, [r2, #0x58]
  00014	e3c334ff	 bic         r3, r3, #0xFF, 8
  00018	e5823058	 str         r3, [r2, #0x58]
  0001c	e5942004	 ldr         r2, [r4, #4]
  00020	e5923070	 ldr         r3, [r2, #0x70]
  00024	e3c3300c	 bic         r3, r3, #0xC
  00028	e5823070	 str         r3, [r2, #0x70]
  0002c	e5942004	 ldr         r2, [r4, #4]
  00030	e592300c	 ldr         r3, [r2, #0xC]
  00034	e383320d	 orr         r3, r3, #0xD, 4
  00038	e582300c	 str         r3, [r2, #0xC]
  0003c	e5942004	 ldr         r2, [r4, #4]
  00040	e592310c	 ldr         r3, [r2, #0x10C]
  00044	e3833802	 orr         r3, r3, #2, 16
  00048	e582310c	 str         r3, [r2, #0x10C]
  0004c	e5942004	 ldr         r2, [r4, #4]
  00050	e5923058	 ldr         r3, [r2, #0x58]
  00054	e3833451	 orr         r3, r3, #0x51, 8
  00058	e5823058	 str         r3, [r2, #0x58]
  0005c	e5942004	 ldr         r2, [r4, #4]
  00060	e5923070	 ldr         r3, [r2, #0x70]
  00064	e3833004	 orr         r3, r3, #4
  00068	e5823070	 str         r3, [r2, #0x70]
  0006c	e5940024	 ldr         r0, [r4, #0x24]
  00070	eb000000	 bl          XllpOstDelayMicroSeconds

; 66   : 
; 67   : //  ensuring the I2S clock is on
; 68   : 	(pDeviceContext->pClockReg)->cken |= XLLP_CLKEN_I2S;

  00074	e5942010	 ldr         r2, [r4, #0x10]

; 69   :     XllpOstDelayMicroSeconds( pDeviceContext->pOSTRegs,10);

  00078	e3a0100a	 mov         r1, #0xA
  0007c	e5923004	 ldr         r3, [r2, #4]
  00080	e3833c01	 orr         r3, r3, #1, 24
  00084	e5823004	 str         r3, [r2, #4]
  00088	e5940024	 ldr         r0, [r4, #0x24]
  0008c	eb000000	 bl          XllpOstDelayMicroSeconds

; 70   : 
; 71   : ////     EdbgOutputDebugString ( "after init, GPDR0  is %x\r\n", (pDeviceContext->pGpioReg)->GPDR0 );
; 72   : 	//EdbgOutputDebugString ( "after init, GPDR3  is %x\r\n", (pDeviceContext->pGpioReg)->GPDR3);
; 73   : 	//EdbgOutputDebugString ( "after init, GAFR0_U  is %x\r\n", (pDeviceContext->pGpioReg)->GAFR0_U );
; 74   : 	//EdbgOutputDebugString ( "after init, GAFR3_U  is %x\r\n", (pDeviceContext->pGpioReg)->GAFR3_U  );
; 75   : //  turning on the amp for output of sound
; 76   : //todo: find this define, it didn't work for me
; 77   : 	//Bcr->MISCWR2 &= ~(XLLP_BCR_MISCWR2_I2S_SPKROFF |XLLP_BCR_MISCWR2_AC97_SPKROFF);
; 78   : 
; 79   : //   choose the normal I2S mode of operation
; 80   : 	(pDeviceContext->pPCMReg)->SACR1 |= XLLP_SACR1_DREC ; 

  00090	e5942008	 ldr         r2, [r4, #8]

; 81   : 	(pDeviceContext->pPCMReg)->SACR1 &= ~(XLLP_SACR1_AMSL | XLLP_SACR1_DRPL |XLLP_SACR1_ENLBF); 
; 82   : //   priming Transmit IO
; 83   :      (pDeviceContext->pPCMReg)->SAICR |= XLLP_SAICR_TUR;
; 84   : 	 for (k=0; k<16; k++)

  00094	e3a01000	 mov         r1, #0
  00098	e5923004	 ldr         r3, [r2, #4]
  0009c	e3833008	 orr         r3, r3, #8
  000a0	e5823004	 str         r3, [r2, #4]
  000a4	e5942008	 ldr         r2, [r4, #8]
  000a8	e5923004	 ldr         r3, [r2, #4]
  000ac	e3c33031	 bic         r3, r3, #0x31
  000b0	e5823004	 str         r3, [r2, #4]
  000b4	e5942008	 ldr         r2, [r4, #8]
  000b8	e5923018	 ldr         r3, [r2, #0x18]
  000bc	e3833020	 orr         r3, r3, #0x20
  000c0	e5823018	 str         r3, [r2, #0x18]
  000c4		 |$L1248|

; 85   :         (pDeviceContext->pPCMReg)->SADR = (k<<15 | k);

  000c4	e5942008	 ldr         r2, [r4, #8]
  000c8	e1813781	 orr         r3, r1, r1, lsl #15
  000cc	e2811001	 add         r1, r1, #1
  000d0	e5823080	 str         r3, [r2, #0x80]
  000d4	e3510010	 cmp         r1, #0x10
  000d8	bafffff9	 blt         |$L1248|

; 86   : 
; 87   : //   enable I2SLINK, maintain the bit clock direction
; 88   : 
; 89   : 	 (pDeviceContext->pPCMReg)->SACR0 = 0;

  000dc	e5943008	 ldr         r3, [r4, #8]
  000e0	e3a02000	 mov         r2, #0

; 90   : 
; 91   :     (pDeviceContext->pPCMReg)->SACR0 |= (XLLP_SACR0_ENB |XLLP_SACR0_BCKD | (0x8<<8) ); 

  000e4	e3a01b02	 mov         r1, #2, 22
  000e8	e5832000	 str         r2, [r3]
  000ec	e5942008	 ldr         r2, [r4, #8]
  000f0	e3811005	 orr         r1, r1, #5

; 92   : 
; 93   :     (pDeviceContext->pPCMReg)->SADIV = 0x34; //appx 11.025KHZ

  000f4	e3a0e034	 mov         lr, #0x34

; 94   : 
; 95   : //   programming the Transmit Threshold
; 96   : //	 (pDeviceContext->pPCMReg)->SACR0 |= 0xC00;
; 97   : 
; 98   :   //EdbgOutputDebugString ( "after init, SACR0  is %x\r\n", myDeviceContext.pPCMReg->SACR0 );
; 99   : //EdbgOutputDebugString ( "after init, status  is %x\r\n", myDeviceContext.pPCMReg->SASR0 );
; 100  :   
; 101  : return XLLP_ACODEC_SUCCESS;

  000f8	e5923000	 ldr         r3, [r2]
  000fc	e3a00000	 mov         r0, #0
  00100	e1833001	 orr         r3, r3, r1
  00104	e5823000	 str         r3, [r2]
  00108	e5943008	 ldr         r3, [r4, #8]
  0010c	e583e060	 str         lr, [r3, #0x60]

; 102  : }

  00110	e8bd4010	 ldmia       sp!, {r4, lr}
  00114	e12fff1e	 bx          lr
  00118		 |$M1266|

			 ENDP  ; |XllpI2sACodecInit|

	END