xllp_intc.lst
来自「pxa270为硬件平台的wince操作系统XLLP驱动源码」· LST 代码 · 共 530 行 · 第 1/3 页
LST
530 行
328 00000000 xlli_SWCR_offset EQU (0x28) ; Stopwatch Counter Register
329 00000000 xlli_SWAR1_offset EQU (0x2C) ; Stopwatch Alarm Register 1
330 00000000 xlli_SWAR2_offset EQU (0x30) ; Stopwatch Alarm Register 2
331 00000000 xlli_PICR_offset EQU (0x34) ; Periodic Interrupt Counter Register
332 00000000 xlli_PIAR_offset EQU (0x38) ; Periodic Interrupt Alarm Register
333 00000000
334 00000000
335 00000000 ; Oscillator Controller bit defs
336 00000000
337 00000000 xlli_OSCC_OOK EQU (0x01) ; Oscillator OK bit
338 00000000 xlli_OSCC_OON EQU (0x02) ; Timekeeping (32.768KHz) Osc bit
339 00000000 xlli_OSCC_TOUT_EN EQU (0x04) ; Timekeeping Output enable
340 00000000 xlli_OSCC_PIO_EN EQU (0x08) ; Processor Oscillator Output Enable
341 00000000 xlli_OSCC_CRI EQU (0x10) ; Processor Oscillator Output Enable
342 00000000
343 00000000 ;
344 00000000 ; Coprocessor 15 data bits
345 00000000 ;
346 00000000
347 00000000 xlli_control_icache EQU (0x1000) ; bit 12 - i-cache bit
348 00000000 xlli_control_btb EQU (0x0800) ; bit 11 - btb bit
349 00000000 xlli_control_r EQU (0x0200) ; Bit 9
350 00000000 xlli_control_s EQU (0x0100) ; Bit 8
351 00000000 xlli_control_dcache EQU (0x0004) ; Bit 2 - d-cache bit
352 00000000 xlli_control_mmu EQU (0x0001) ; Bit 0 - MMU bit
353 00000000
354 00000000
355 00000000 ;
356 00000000 ; CP 15 related settings
357 00000000 ;
358 00000000
359 00000000 xlli_PID EQU (0x00)
360 00000000 xlli_DACR EQU (0x01)
361 00000000 xlli_CONTROL_DCACHE EQU (0x04)
362 00000000 xlli_CONTROL_MINIDATA_01 EQU (0x10)
363 00000000 xlli_CONTROL_BTB EQU (0x800) ; Brach Target Buffer bit
364 00000000
365 00000000 ;
366 00000000 ; register bit masks - RCSR
367 00000000 ;
368 00000000 xlli_RCSR_HWR EQU (0x01)
369 00000000 xlli_RCSR_WDR EQU (0x02)
370 00000000 xlli_RCSR_SMR EQU (0x04)
371 00000000 xlli_RCSR_GPR EQU (0x08)
372 00000000 xlli_RCSR_ALL EQU (0xF)
373 00000000
374 00000000
375 00000000 ;
376 00000000 ; CPSR Processor constants
377 00000000
378 00000000 xlli_CPSR_Mode_MASK EQU (0x0000001F)
379 00000000 xlli_CPSR_Mode_USR EQU (0x10)
380 00000000 xlli_CPSR_Mode_FIQ EQU (0x11)
381 00000000 xlli_CPSR_Mode_IRQ EQU (0x12)
382 00000000 xlli_CPSR_Mode_SVC EQU (0x13)
383 00000000 xlli_CPSR_Mode_ABT EQU (0x17)
384 00000000 xlli_CPSR_Mode_UND EQU (0x1B)
385 00000000 xlli_CPSR_Mode_SYS EQU (0x1F)
386 00000000
387 00000000 xlli_CPSR_I_Bit EQU (0x80)
388 00000000 xlli_CPSR_F_Bit EQU (0x40)
389 00000000
390 00000000
391 00000000 xlli_PWRMODE_SLEEP EQU (0x00000003) ; Value for cp14: Reg7 to induce sleep.
392 00000000 ; Bit settings
393 00000000 ;
394 00000000 xlli_BIT_0 EQU 0x00000001
395 00000000 xlli_BIT_1 EQU 0x00000002
396 00000000 xlli_BIT_2 EQU 0x00000004
397 00000000 xlli_BIT_3 EQU 0x00000008
398 00000000 xlli_BIT_4 EQU 0x00000010
399 00000000 xlli_BIT_5 EQU 0x00000020
400 00000000 xlli_BIT_6 EQU 0x00000040
401 00000000 xlli_BIT_7 EQU 0x00000080
402 00000000 xlli_BIT_8 EQU 0x00000100
403 00000000 xlli_BIT_9 EQU 0x00000200
404 00000000 xlli_BIT_10 EQU 0x00000400
405 00000000 xlli_BIT_11 EQU 0x00000800
406 00000000 xlli_BIT_12 EQU 0x00001000
407 00000000 xlli_BIT_13 EQU 0x00002000
408 00000000 xlli_BIT_14 EQU 0x00004000
409 00000000 xlli_BIT_15 EQU 0x00008000
410 00000000 xlli_BIT_16 EQU 0x00010000
411 00000000 xlli_BIT_17 EQU 0x00020000
412 00000000 xlli_BIT_18 EQU 0x00040000
413 00000000 xlli_BIT_19 EQU 0x00080000
414 00000000 xlli_BIT_20 EQU 0x00100000
415 00000000 xlli_BIT_21 EQU 0x00200000
416 00000000 xlli_BIT_22 EQU 0x00400000
417 00000000 xlli_BIT_23 EQU 0x00800000
418 00000000 xlli_BIT_24 EQU 0x01000000
419 00000000 xlli_BIT_25 EQU 0x02000000
420 00000000 xlli_BIT_26 EQU 0x04000000
421 00000000 xlli_BIT_27 EQU 0x08000000
422 00000000 xlli_BIT_28 EQU 0x10000000
423 00000000 xlli_BIT_29 EQU 0x20000000
424 00000000 xlli_BIT_30 EQU 0x40000000
425 00000000 xlli_BIT_31 EQU 0x80000000
426 00000000 END
27 00000000
28 00000000 ;
29 00000000 ; List of primitive functions in this module:
30 00000000 ;
31 00000000 EXPORT XllpIntcDisableInts
32 00000000 EXPORT XllpIntcRestoreInts
33 00000000
34 AREA |.text|, CODE, READONLY, ALIGN=5 ; Align =5 required for "ALIGN 32" to work
35 00000000
36 00000000
37 00000000
38 00000000
39 00000000 ;;;;;;;;;;;;;;;;;;;;;;;;;;;
40 00000000 ;;
41 00000000 ;; UINT32 XllpIntcDisableInts (void)
42 00000000 ;;
43 00000000 ;; Disable IRQ and FIQ interrupts by setting the I+F bits in the CPSR.
44 00000000 ;;
45 00000000 ;; Returns (R0): the state of the I+F bits before they were set
46 00000000 ;;
47 00000000 ;; Assumes caller is running in privileged mode.
48 00000000 ;;
49 00000000
50 00000000 XllpIntcDisableInts FUNCTION
51 00000000
52 00000000 e3a010c0 mov r1, #(xlli_CPSR_I_Bit:OR:xlli_CPSR_F_Bit)
53 00000004 e10f2000 mrs r2, cpsr
54 00000008 e0020001 and r0, r2, r1 ; This is the return with the current int flags
55 0000000c e1822001 orr r2, r2, r1
56 00000010 e121f002 msr cpsr_c, r2 ; Only interested in control fields
57 00000014
58 00000014 IF :DEF: Interworking
59 00000014 IF Interworking :LOR: Thumbing
60 00000014 e12fff1e bx lr
61 00000018 ELSE
63 00000018 ENDIF
64 00000018 ELSE
66 00000018 ENDIF
67 00000018
68 00000018 ENDFUNC
69 00000018
70 00000018
71 00000018 ;;;;;;;;;;;;;;;;;;;;;;;;;;;
72 00000018 ;;
73 00000018 ;; void XllpIntcRestoreInts (UINT32)
74 00000018 ;;
75 00000018 ;; Set the I+F bits in the CPSR to the values received in R0.
76 00000018 ;; - Protects against changing any other bits the CPSR.
77 00000018 ;; - If the value returned by pmDisableInts() is used as the parameter,
78 00000018 ;; this function restores the interrupt enable/disable state to
79 00000018 ;; that which existed at the time pmDisableInts() was invoked.
80 00000018 ;;
81 00000018 ;; Assumes caller is running in privileged mode.
82 00000018 ;;
83 00000018
84 00000018 XllpIntcRestoreInts FUNCTION
85 00000018
86 00000018 e3a010c0 mov r1, #(xlli_CPSR_I_Bit:OR:xlli_CPSR_F_Bit)
87 0000001c e0000001 and r0, r0, r1 ; Isolate the I+F bits
88 00000020 e10f2000 mrs r2, cpsr ; Get existing settings
89 00000024 e1c22001 bic r2, r2, r1 ; Clear out the flag locations
90 00000028 e1822000 orr r2, r2, r0 ; Set the restored flags in place
91 0000002c e121f002 msr cpsr_c, r2 ; Only interested in control fields
92 00000030
93 00000030 IF :DEF: Interworking
94 00000030 IF Interworking :LOR: Thumbing
95 00000030 e12fff1e bx lr
96 00000034 ELSE
98 00000034 ENDIF
99 00000034 ELSE
101 00000034 ENDIF
102 00000034
103 00000034 ENDFUNC
104 00000034
105 00000034 END
Assembly terminated, errors: 0, warnings: 0
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