📄 xllp_dvm.cod
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; 201 :
; 202 :
; 203 : v_pPmgrReg->PCFR &= ~XLLP_PCFR_FVC; // ~PCFR_FVC;
00010 e594301c ldr r3, [r4, #0x1C]
; 204 : v_pPmgrReg->PVCR &=0xFFFFF07F; //no delay is necessary
; 205 : v_pPmgrReg->PVCR &= 0xFFFFFF80; //clear slave address
; 206 : v_pPmgrReg->PVCR |= VOLTAGE_REGULATOR_ADDRESS; //set slave address
; 207 :
; 208 : v_pPmgrReg->PVCR &= 0xFE0FFFFF; //clear read pointer 0
00014 e1a0e800 mov lr, r0, lsl #16
00018 e20000ff and r0, r0, #0xFF
0001c e3c33b01 bic r3, r3, #1, 22
00020 e584301c str r3, [r4, #0x1C]
00024 e5943040 ldr r3, [r4, #0x40]
00028 e2842080 add r2, r4, #0x80
0002c e3a01020 mov r1, #0x20
00030 e3c33d3e bic r3, r3, #0x3E, 26
00034 e5843040 str r3, [r4, #0x40]
00038 e5943040 ldr r3, [r4, #0x40]
0003c e3c3307f bic r3, r3, #0x7F
00040 e5843040 str r3, [r4, #0x40]
00044 e5943040 ldr r3, [r4, #0x40]
00048 e3833020 orr r3, r3, #0x20
0004c e5843040 str r3, [r4, #0x40]
00050 e5943040 ldr r3, [r4, #0x40]
00054 e3c3361f bic r3, r3, #0x1F, 12
00058 e5843040 str r3, [r4, #0x40]
0005c |$L1007|
; 209 :
; 210 :
; 211 : //Clear SQC DCE and MBC
; 212 : for(i=0; i<32; i++)
; 213 : {
; 214 : v_pPmgrReg->PCMDn[i] &= ~XLLP_PCMD_SQC;
0005c e5923000 ldr r3, [r2]
00060 e2511001 subs r1, r1, #1
00064 e3c33c03 bic r3, r3, #3, 24
00068 e5823000 str r3, [r2]
; 215 : v_pPmgrReg->PCMDn[i] &= ~XLLP_PCMD_DCE; //Clear DCE
0006c e5923000 ldr r3, [r2]
00070 e3c33b02 bic r3, r3, #2, 22
00074 e5823000 str r3, [r2]
; 216 : v_pPmgrReg->PCMDn[i] &= ~XLLP_PCMD_MBC; //Clear MBC
00078 e5923000 ldr r3, [r2]
0007c e3c33a01 bic r3, r3, #1, 20
00080 e4823004 str r3, [r2], #4
00084 1afffff4 bne |$L1007|
; 217 : }
; 218 :
; 219 : //Set MBC bit
; 220 :
; 221 : v_pPmgrReg->PCMDn[0] |= XLLP_PCMD_MBC;
00088 e5943080 ldr r3, [r4, #0x80]
; 222 : v_pPmgrReg->PCMDn[1] |= XLLP_PCMD_MBC;
; 223 :
; 224 : //indicate the last byte of this command is holded in this register
; 225 : v_pPmgrReg->PCMDn[2] &=~ XLLP_PCMD_MBC;
0008c e3833a01 orr r3, r3, #1, 20
00090 e5843080 str r3, [r4, #0x80]
00094 e5943084 ldr r3, [r4, #0x84]
; 226 :
; 227 : //indicate this is the first and last command also
; 228 : v_pPmgrReg->PCMDn[0] |= XLLP_PCMD_LC ; //LC bit
; 229 : v_pPmgrReg->PCMDn[1] |= XLLP_PCMD_LC ;
; 230 : v_pPmgrReg->PCMDn[2] |= XLLP_PCMD_LC ;
; 231 :
; 232 : //programming the command data bits
; 233 : v_pPmgrReg->PCMDn[0] &= 0xFFFFFF00;
00098 e3833a01 orr r3, r3, #1, 20
0009c e5843084 str r3, [r4, #0x84]
000a0 e5943088 ldr r3, [r4, #0x88]
; 234 : v_pPmgrReg->PCMDn[0] |= dataArray[0];
; 235 :
; 236 : v_pPmgrReg->PCMDn[1] &= 0xFFFFFF00;
; 237 : v_pPmgrReg->PCMDn[1] |= dataArray[1];
; 238 :
; 239 : v_pPmgrReg->PCMDn[2] &= 0xFFFFFF00;
000a4 e3c33a01 bic r3, r3, #1, 20
000a8 e5843088 str r3, [r4, #0x88]
000ac e5943080 ldr r3, [r4, #0x80]
; 240 : v_pPmgrReg->PCMDn[2] |= dataArray[2];
; 241 :
; 242 : //indicate this is the first and last command also
; 243 : v_pPmgrReg->PCMDn[0] |= XLLP_PCMD_LC; //LC bit
; 244 : v_pPmgrReg->PCMDn[1] |= XLLP_PCMD_LC;
; 245 : v_pPmgrReg->PCMDn[2] |= XLLP_PCMD_LC;
; 246 :
; 247 : //programming the command data bits
; 248 : v_pPmgrReg->PCMDn[0] &= 0xFFFFFF00;
; 249 : v_pPmgrReg->PCMDn[0] |= dataArray[0];
; 250 :
; 251 : v_pPmgrReg->PCMDn[1] &= 0xFFFFFF00;
000b0 e3833b01 orr r3, r3, #1, 22
000b4 e5843080 str r3, [r4, #0x80]
000b8 e5943084 ldr r3, [r4, #0x84]
; 252 : v_pPmgrReg->PCMDn[1] |= dataArray[1];
; 253 :
; 254 : v_pPmgrReg->PCMDn[2] &= 0xFFFFFF00;
000bc e3833b01 orr r3, r3, #1, 22
000c0 e5843084 str r3, [r4, #0x84]
000c4 e5943088 ldr r3, [r4, #0x88]
000c8 e3833b01 orr r3, r3, #1, 22
000cc e5843088 str r3, [r4, #0x88]
000d0 e5943080 ldr r3, [r4, #0x80]
000d4 e3c330ff bic r3, r3, #0xFF
000d8 e5843080 str r3, [r4, #0x80]
000dc e5943080 ldr r3, [r4, #0x80]
000e0 e5843080 str r3, [r4, #0x80]
000e4 e5943084 ldr r3, [r4, #0x84]
000e8 e3c330ff bic r3, r3, #0xFF
000ec e5843084 str r3, [r4, #0x84]
000f0 e5943084 ldr r3, [r4, #0x84]
000f4 e1833000 orr r3, r3, r0
000f8 e5843084 str r3, [r4, #0x84]
000fc e5943088 ldr r3, [r4, #0x88]
00100 e3c330ff bic r3, r3, #0xFF
00104 e5843088 str r3, [r4, #0x88]
00108 e5943088 ldr r3, [r4, #0x88]
0010c e1833c2e orr r3, r3, lr, lsr #24
00110 e5843088 str r3, [r4, #0x88]
00114 e5943080 ldr r3, [r4, #0x80]
00118 e3833b01 orr r3, r3, #1, 22
0011c e5843080 str r3, [r4, #0x80]
00120 e5943084 ldr r3, [r4, #0x84]
00124 e3833b01 orr r3, r3, #1, 22
00128 e5843084 str r3, [r4, #0x84]
0012c e5943088 ldr r3, [r4, #0x88]
00130 e3833b01 orr r3, r3, #1, 22
00134 e5843088 str r3, [r4, #0x88]
00138 e5943080 ldr r3, [r4, #0x80]
0013c e3c330ff bic r3, r3, #0xFF
00140 e5843080 str r3, [r4, #0x80]
00144 e5943080 ldr r3, [r4, #0x80]
00148 e5843080 str r3, [r4, #0x80]
0014c e5943084 ldr r3, [r4, #0x84]
00150 e3c330ff bic r3, r3, #0xFF
00154 e5843084 str r3, [r4, #0x84]
00158 e5943084 ldr r3, [r4, #0x84]
0015c e1833000 orr r3, r3, r0
00160 e5843084 str r3, [r4, #0x84]
00164 e5943088 ldr r3, [r4, #0x88]
00168 e3c330ff bic r3, r3, #0xFF
0016c e5843088 str r3, [r4, #0x88]
; 255 : v_pPmgrReg->PCMDn[2] |= dataArray[2];
00170 e5943088 ldr r3, [r4, #0x88]
00174 e1833c2e orr r3, r3, lr, lsr #24
00178 e5843088 str r3, [r4, #0x88]
; 256 :
; 257 :
; 258 : //Enable Power I2C
; 259 : v_pPmgrReg->PCFR |= XLLP_PCFR_PI2C_EN; //enable Pwr I2C
0017c e594301c ldr r3, [r4, #0x1C]
00180 e3833040 orr r3, r3, #0x40
00184 e584301c str r3, [r4, #0x1C]
; 260 :
; 261 : //Execute voltage change sequence
; 262 : XllpXSC1ChangeVoltage( ); //set VC on the PWRMODE on CP14
00188 eb000000 bl XllpXSC1ChangeVoltage
0018c |$L1011|
; 263 :
; 264 : while ( ( (v_pPmgrReg->PVCR) & XLLP_PVCR_VCSA) !=0 );
0018c e5943040 ldr r3, [r4, #0x40]
00190 e3130901 tst r3, #1, 18
00194 1afffffc bne |$L1011|
; 265 :
; 266 :
; 267 : }
00198 e8bd4010 ldmia sp!, {r4, lr}
0019c e12fff1e bx lr
001a0 |$M1116|
ENDP ; |XllpVMSetVoltage|
EXPORT |XllpFreqVoltageChange|
00000 AREA |.text| { |XllpFreqVoltageChange| }, CODE, ARM, SELECTION=1 ; comdat noduplicate
00000 AREA |.pdata$$XllpFreqVoltageChange|, PDATA, SELECTION=5, ASSOC=|.text| { |XllpFreqVoltageChange| } ; comdat associative
|$T1135| DCD |$L1134|
DCD 0x40005303
; Function compile flags: /Ogsy
00000 AREA |.text| { |XllpFreqVoltageChange| }, CODE, ARM, SELECTION=1 ; comdat noduplicate
00000 |XllpFreqVoltageChange| PROC
; 290 : {
00000 |$L1134|
00000 e1a0c00d mov r12, sp
00004 e92d000c stmdb sp!, {r2, r3}
00008 e92d5070 stmdb sp!, {r4 - r6, r12, lr}
0000c |$M1132|
0000c e1a05000 mov r5, r0
; 291 : XLLP_UINT32_T newCLKCFGValue = 0;
; 292 : XLLP_UINT32_T CLKCFGValue = 0;
; 293 : XLLP_UINT32_T ReadPointer = 0, i=0;
; 294 : XLLP_UINT32_T NumOfBytes = 3;
; 295 : XLLP_UINT32_T dataArray[3];
; 296 : XLLP_UINT32_T LMulti, NMulti;
; 297 :
; 298 :
; 299 : dataArray[0] = 0; //Command 0
; 300 : dataArray[1] = (combo_param.DacValue & 0x000000FF);
; 301 : dataArray[2] = (combo_param.DacValue & 0x0000FF00)>>8;
; 302 :
; 303 : NMulti = 2; //run mode, N=2
; 304 : LMulti = combo_param.frequency / PRIMARY_CLOCK_FREQ;
00010 e59fe130 ldr lr, [pc, #0x130]
; 305 :
; 306 : //set up the new frequency mulitipliers, N and L
; 307 : v_pClkReg->cccr = (NMulti<<7) | LMulti;
; 308 :
; 309 : newCLKCFGValue = (XLLP_CLKCFG_F | combo_param.fastbus_mode<<3);
; 310 :
; 311 : //votlage change configureation
; 312 : v_pPmgrReg->PVCR = 0;
00014 e3a00000 mov r0, #0
00018 e08e4e92 umull r4, lr, r2, lr
; 313 : v_pPmgrReg->PCFR &= ~XLLP_PCFR_FVC; // First disable Frequency/Voltage Sequence
; 314 : v_pPmgrReg->PVCR &= 0xFFFFF07F; //no delay is necessary
; 315 : v_pPmgrReg->PVCR |= 0x20; //set Slave address
; 316 : v_pPmgrReg->PVCR &= 0xFE0FFFFF; //clear read pointer 0
0001c e2852080 add r2, r5, #0x80
00020 e1a0e12e mov lr, lr, lsr #2
00024 e38eec01 orr lr, lr, #1, 24
00028 e581e000 str lr, [r1]
0002c e5850040 str r0, [r5, #0x40]
00030 e595101c ldr r1, [r5, #0x1C]
00034 e1a00183 mov r0, r3, lsl #3
00038 e59de020 ldr lr, [sp, #0x20]
0003c e3c11b01 bic r1, r1, #1, 22
00040 e585101c str r1, [r5, #0x1C]
00044 e5951040 ldr r1, [r5, #0x40]
00048 e1a0680e mov r6, lr, lsl #16
0004c e20ee0ff and lr, lr, #0xFF
00050 e3c13d3e bic r3, r1, #0x3E, 26
00054 e5853040 str r3, [r5, #0x40]
00058 e5953040 ldr r3, [r5, #0x40]
0005c e3a01020 mov r1, #0x20
00060 e3833020 orr r3, r3, #0x20
00064 e5853040 str r3, [r5, #0x40]
00068 e5953040 ldr r3, [r5, #0x40]
0006c e3c3361f bic r3, r3, #0x1F, 12
00070 e5853040 str r3, [r5, #0x40]
00074 |$L1029|
; 317 :
; 318 :
; 319 :
; 320 :
; 321 : //Clear SQC DCE and MBC
; 322 : for(i=0; i<32; i++)
; 323 : {
; 324 : v_pPmgrReg->PCMDn[i] &= ~XLLP_PCMD_SQC;
00074 e5923000 ldr r3, [r2]
00078 e2511001 subs r1, r1, #1
0007c e3c33c03 bic r3, r3, #3, 24
00080 e5823000 str r3, [r2]
; 325 : v_pPmgrReg->PCMDn[i] &= ~XLLP_PCMD_DCE; //Clear DCE
00084 e5923000 ldr r3, [r2]
00088 e3c33b02 bic r3, r3, #2, 22
0008c e5823000 str r3, [r2]
; 326 : v_pPmgrReg->PCMDn[i] &= ~XLLP_PCMD_MBC; //Clear MBC
00090 e5923000 ldr r3, [r2]
00094 e3c33a01 bic r3, r3, #1, 20
00098 e4823004 str r3, [r2], #4
0009c 1afffff4 bne |$L1029|
; 327 : }
; 328 :
; 329 : //Set MBC bit
; 330 :
; 331 : v_pPmgrReg->PCMDn[0] |= XLLP_PCMD_MBC;
000a0 e5953080 ldr r3, [r5, #0x80]
; 332 : v_pPmgrReg->PCMDn[1] |= XLLP_PCMD_MBC;
; 333 :
; 334 : //indicate the last byte of this command is holded in this register
; 335 : v_pPmgrReg->PCMDn[2] &=~ XLLP_PCMD_MBC ;
; 336 :
; 337 : //indicate this is the first and last command also
; 338 : v_pPmgrReg->PCMDn[0] |= XLLP_PCMD_LC; //LC bit
; 339 : v_pPmgrReg->PCMDn[1] |= XLLP_PCMD_LC;
; 340 : v_pPmgrReg->PCMDn[2] |= XLLP_PCMD_LC;
; 341 :
; 342 : //programming the command data bits
; 343 : v_pPmgrReg->PCMDn[0] &= 0xFFFFFF00;
; 344 : v_pPmgrReg->PCMDn[0] |= dataArray[0];
; 345 :
; 346 : v_pPmgrReg->PCMDn[1] &= 0xFFFFFF00;
; 347 : v_pPmgrReg->PCMDn[1] |= dataArray[1];
; 348 :
; 349 : v_pPmgrReg->PCMDn[2] &= 0xFFFFFF00;
; 350 : v_pPmgrReg->PCMDn[2] |= dataArray[2];
; 351 :
; 352 : v_pPmgrReg->PCFR |= (XLLP_PCFR_PI2C_EN | XLLP_PCFR_FVC); //PCFR_PI2C_EN; //enable Pwr I2C
; 353 :
; 354 : //set CLKCFG reigster in CP14 to initiate the freq/voltage change sequence
; 355 : XllpXSC1FreqChange(newCLKCFGValue);
000a4 e3800002 orr r0, r0, #2
000a8 e3833a01 orr r3, r3, #1, 20
000ac e5853080 str r3, [r5, #0x80]
000b0 e5953084 ldr r3, [r5, #0x84]
000b4 e3833a01 orr r3, r3, #1, 20
000b8 e5853084 str r3, [r5, #0x84]
000bc e5953088 ldr r3, [r5, #0x88]
000c0 e3c33a01 bic r3, r3, #1, 20
000c4 e5853088 str r3, [r5, #0x88]
000c8 e5953080 ldr r3, [r5, #0x80]
000cc e3833b01 orr r3, r3, #1, 22
000d0 e5853080 str r3, [r5, #0x80]
000d4 e5953084 ldr r3, [r5, #0x84]
000d8 e3833b01 orr r3, r3, #1, 22
000dc e5853084 str r3, [r5, #0x84]
000e0 e5953088 ldr r3, [r5, #0x88]
000e4 e3833b01 orr r3, r3, #1, 22
000e8 e5853088 str r3, [r5, #0x88]
000ec e5953080 ldr r3, [r5, #0x80]
000f0 e3c330ff bic r3, r3, #0xFF
000f4 e5853080 str r3, [r5, #0x80]
000f8 e5953080 ldr r3, [r5, #0x80]
000fc e5853080 str r3, [r5, #0x80]
00100 e5953084 ldr r3, [r5, #0x84]
00104 e3c330ff bic r3, r3, #0xFF
00108 e5853084 str r3, [r5, #0x84]
0010c e5953084 ldr r3, [r5, #0x84]
00110 e183300e orr r3, r3, lr
00114 e5853084 str r3, [r5, #0x84]
00118 e5953088 ldr r3, [r5, #0x88]
0011c e3c330ff bic r3, r3, #0xFF
00120 e5853088 str r3, [r5, #0x88]
00124 e5953088 ldr r3, [r5, #0x88]
00128 e1833c26 orr r3, r3, r6, lsr #24
0012c e5853088 str r3, [r5, #0x88]
00130 e595301c ldr r3, [r5, #0x1C]
00134 e3833d11 orr r3, r3, #0x11, 26
00138 e585301c str r3, [r5, #0x1C]
0013c eb000000 bl XllpXSC1FreqChange
; 356 :
; 357 :
; 358 : }
00140 e89d6070 ldmia sp, {r4 - r6, sp, lr}
00144 e12fff1e bx lr
00148 |$L1137|
00148 4ec4ec4f DCD 0x4ec4ec4f
0014c |$M1133|
ENDP ; |XllpFreqVoltageChange|
END
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