📄 xllp_acodec.cod
字号:
00000 e92d41f0 stmdb sp!, {r4 - r8, lr}
00004 |$M1688|
00004 e1a05001 mov r5, r1
00008 e3500000 cmp r0, #0
; 376 : XLLP_ACODEC_ERROR_T retval=XLLP_ACODEC_SUCCESS;
0000c e3a06000 mov r6, #0
; 377 :
; 378 : if (Owner==XLLP_NEARSIDE)
00010 1a000052 bne |$L1576|
; 379 : {
; 380 : //GPIO configuration for enabling SSP path from Bulverde to AKM2440
; 381 : if(pDeviceContext->pGpioReg)
00014 e5953004 ldr r3, [r5, #4]
00018 e3530000 cmp r3, #0
0001c 0a000026 beq |$L1577|
; 382 : {
; 383 : (pDeviceContext->pGpioReg)->GAFR0_U &= ~XLLP_GPIO_AF_BIT_SSP2_SSPRXD2_MASK;
00020 e1a02003 mov r2, r3
; 384 : (pDeviceContext->pGpioReg)->GAFR2_U &=~XLLP_GPIO_AF_BIT_SSPFRM2_MASK;
00024 e5923058 ldr r3, [r2, #0x58]
; 385 : (pDeviceContext->pGpioReg)->GPDR0 |= XLLP_GPIO_BIT_SSPCLK2 | XLLP_GPIO_BIT_SSPTXD2;
00028 e3a00501 mov r0, #1, 10
0002c e3800a02 orr r0, r0, #2, 20
; 386 : (pDeviceContext->pGpioReg)->GPDR0 |= XXLP_GPIO_BIT_SSP2_SSPRXD2; //GPIO29
; 387 : (pDeviceContext->pGpioReg)->GPDR2 |= XLLP_GPIO_BIT_SSPFRM2; //GPIO 88
; 388 : (pDeviceContext->pGpioReg)->GAFR0_L |= XLLP_GPIO_AF_BIT_SSPTXD2; //GPIO 13
; 389 : (pDeviceContext->pGpioReg)->GAFR0_U |= XLLP_GPIO_AF_BIT_SSP2_SSPRXD2; //GPIO29
; 390 : (pDeviceContext->pGpioReg)->GAFR0_U |= XLLP_GPIO_AF_BIT_SSPCLK2; //GPIO 22
; 391 : (pDeviceContext->pGpioReg)->GAFR2_U |= XLLP_GPIO_AF_BIT_SSPFRM2; //GPIO 88
; 392 :
; 393 : retval = XLLP_ACODEC_SUCCESS;
00030 e3c33303 bic r3, r3, #3, 6
00034 e5823058 str r3, [r2, #0x58]
00038 e5952004 ldr r2, [r5, #4]
0003c e3a06000 mov r6, #0
00040 e5923068 ldr r3, [r2, #0x68]
00044 e3c33803 bic r3, r3, #3, 16
00048 e5823068 str r3, [r2, #0x68]
0004c e5952004 ldr r2, [r5, #4]
00050 e592300c ldr r3, [r2, #0xC]
00054 e1833000 orr r3, r3, r0
00058 e582300c str r3, [r2, #0xC]
0005c e5952004 ldr r2, [r5, #4]
00060 e592300c ldr r3, [r2, #0xC]
00064 e3833202 orr r3, r3, #2, 4
00068 e582300c str r3, [r2, #0xC]
0006c e5952004 ldr r2, [r5, #4]
00070 e5923014 ldr r3, [r2, #0x14]
00074 e3833401 orr r3, r3, #1, 8
00078 e5823014 str r3, [r2, #0x14]
0007c e5952004 ldr r2, [r5, #4]
00080 e5923054 ldr r3, [r2, #0x54]
00084 e3833301 orr r3, r3, #1, 6
00088 e5823054 str r3, [r2, #0x54]
0008c e5952004 ldr r2, [r5, #4]
00090 e5923058 ldr r3, [r2, #0x58]
00094 e3833301 orr r3, r3, #1, 6
00098 e5823058 str r3, [r2, #0x58]
0009c e5952004 ldr r2, [r5, #4]
000a0 e5923058 ldr r3, [r2, #0x58]
000a4 e3833a03 orr r3, r3, #3, 20
000a8 e5823058 str r3, [r2, #0x58]
000ac e5952004 ldr r2, [r5, #4]
000b0 e5923068 ldr r3, [r2, #0x68]
000b4 e3833803 orr r3, r3, #3, 16
000b8 e5823068 str r3, [r2, #0x68]
000bc |$L1577|
; 394 : }
; 395 :
; 396 : // EdbgOutputDebugString ( "In SSP Enable code, GPDR0 is %x\r\n",(pDeviceContext->pGpioReg)->GPDR0 );
; 397 : // EdbgOutputDebugString ( "In SSP Enable code, GPDR2 is %x\r\n",(pDeviceContext->pGpioReg)->GPDR2 );
; 398 : // EdbgOutputDebugString ( "In SSP Enable code, GAFR0_U is %x\r\n",(pDeviceContext->pGpioReg)->GAFR0_U );
; 399 : // EdbgOutputDebugString ( "In SSP Enable code, GAFR0_L is %x\r\n",(pDeviceContext->pGpioReg)->GAFR0_L );
; 400 : // EdbgOutputDebugString ( "In SSP Enable code, GAFR2_U is %x\r\n",(pDeviceContext->pGpioReg)->GAFR2_U );
; 401 : //Configure SSP path
; 402 : //| XXLP_SSCR1_RSRE
; 403 : if(pDeviceContext->pSSPReg)
000bc e5953014 ldr r3, [r5, #0x14]
000c0 e3530000 cmp r3, #0
000c4 0a000023 beq |$L1578|
; 404 : {
; 405 : (pDeviceContext->pSSPReg)->sscr0;
000c8 e1a02003 mov r2, r3
; 406 : (pDeviceContext->pSSPReg)->sscr0 = (XLLP_SSCR0_DSS_16BIT | XLLP_SSCR0_FRF_PSP |XLLP_SSCR0_SCR_128K|XLLP_SSCR0_RIM |XLLP_SSCR0_TIM);
000cc e59f3118 ldr r3, [pc, #0x118]
; 407 : (pDeviceContext->pSSPReg)->sscr0 &= ~(XLLP_SSCR0_EDSS | XLLP_SSCR0_NCS | XLLP_SSCR0_ECS); //due to 16 bit data trnasfer & on_chip clock
000d0 e5920000 ldr r0, [r2]
000d4 e59f110c ldr r1, [pc, #0x10C]
000d8 e5823000 str r3, [r2]
000dc e5952014 ldr r2, [r5, #0x14]
; 408 : (pDeviceContext->pSSPReg)->sscr1 = 0x00000000;
000e0 e3a08000 mov r8, #0
; 409 : (pDeviceContext->pSSPReg)->sscr1 = (XLLP_SSCR1_RWOT |XXLP_SSCR1_RSRE|XLLP_SSCR1_TTE | (0x7<<10) ); //XXLP_SSCR1_RSRE |XXLP_SSCR1_RIE
000e4 e59fe0f8 ldr lr, [pc, #0xF8]
000e8 e5923000 ldr r3, [r2]
; 410 :
; 411 : //(pDeviceContext->pSSPReg)->sscr1 = 0x02000C01; //set RFT is 15 bit 10 - 13
; 412 : (pDeviceContext->pSSPReg)->sspsp = 0x00010005;
000ec e3a04801 mov r4, #1, 16
000f0 e3844005 orr r4, r4, #5
; 413 : (pDeviceContext->pSSPReg)->ssitr = 0;
; 414 : (pDeviceContext->pSSPReg)->ssto = 0x1000;
000f4 e0033001 and r3, r3, r1
000f8 e5823000 str r3, [r2]
000fc e5953014 ldr r3, [r5, #0x14]
00100 e3a07a01 mov r7, #1, 20
; 415 : (pDeviceContext->pClockReg)->cken |=XLLP_CLKEN_SSP2;
; 416 : XllpOstDelayMicroSeconds( pDeviceContext->pOSTRegs,1);
00104 e3a01001 mov r1, #1
00108 e5838004 str r8, [r3, #4]
0010c e5953014 ldr r3, [r5, #0x14]
00110 e583e004 str lr, [r3, #4]
00114 e5953014 ldr r3, [r5, #0x14]
00118 e583402c str r4, [r3, #0x2C]
0011c e5953014 ldr r3, [r5, #0x14]
00120 e583800c str r8, [r3, #0xC]
00124 e5953014 ldr r3, [r5, #0x14]
00128 e5837028 str r7, [r3, #0x28]
0012c e5952010 ldr r2, [r5, #0x10]
00130 e5923004 ldr r3, [r2, #4]
00134 e3833008 orr r3, r3, #8
00138 e5823004 str r3, [r2, #4]
0013c e5950024 ldr r0, [r5, #0x24]
00140 eb000000 bl XllpOstDelayMicroSeconds
; 417 : (pDeviceContext->pSSPReg)->sscr0 |=XLLP_SSCR0_SSE;
00144 e5952014 ldr r2, [r5, #0x14]
00148 e5923000 ldr r3, [r2]
0014c e3833080 orr r3, r3, #0x80
00150 e5823000 str r3, [r2]
; 418 :
; 419 :
; 420 : }
; 421 : else
00154 ea00001e b |$L1580|
00158 |$L1578|
; 422 : retval = XLLP_ACODEC_CONTROLLER_NOT_INITIALIZED;
00158 e3a06006 mov r6, #6
; 423 : }
; 424 : else
0015c ea00001c b |$L1580|
00160 |$L1576|
; 425 : {
; 426 :
; 427 : //Tri-state Bulverde, setting GPIO as input, clear alternative function, not sure that it is real tristate
; 428 : // On Bulverde SSP section, SSCR1, bit 30(TTE) can be used to tristate TXD line. Never try!
; 429 :
; 430 : (pDeviceContext->pGpioReg)->GPDR0 &= ~(XLLP_GPIO_BIT_SSPCLK2 | XLLP_GPIO_BIT_SSPTXD2);
00160 e5951004 ldr r1, [r5, #4]
00164 e59f2074 ldr r2, [pc, #0x74]
; 431 : (pDeviceContext->pGpioReg)->GPDR0 &= ~XXLP_GPIO_BIT_SSP2_SSPRXD2; //GPIO29
00168 e591300c ldr r3, [r1, #0xC]
; 432 : (pDeviceContext->pGpioReg)->GPDR2 &= ~XLLP_GPIO_BIT_SSPFRM2; //GPIO 88
; 433 :
; 434 : (pDeviceContext->pGpioReg)->GAFR0_U &= ~XLLP_GPIO_AF_BIT_SSP2_SSPRXD2_MASK;
0016c e0033002 and r3, r3, r2
00170 e581300c str r3, [r1, #0xC]
00174 e5952004 ldr r2, [r5, #4]
; 435 : (pDeviceContext->pGpioReg)->GAFR0_L &= ~(XLLP_GPIO_AF_BIT_SSPTXD2_MASK);
; 436 : (pDeviceContext->pGpioReg)->GAFR0_U &= ~(XLLP_GPIO_AF_BIT_SSPCLK2);
00178 e592300c ldr r3, [r2, #0xC]
; 437 : (pDeviceContext->pGpioReg)->GAFR2_U &=~XLLP_GPIO_AF_BIT_SSPFRM2_MASK;
0017c e3c33202 bic r3, r3, #2, 4
00180 e582300c str r3, [r2, #0xC]
00184 e5952004 ldr r2, [r5, #4]
00188 e5923014 ldr r3, [r2, #0x14]
0018c e3c33401 bic r3, r3, #1, 8
00190 e5823014 str r3, [r2, #0x14]
00194 e5952004 ldr r2, [r5, #4]
00198 e5923058 ldr r3, [r2, #0x58]
0019c e3c33303 bic r3, r3, #3, 6
001a0 e5823058 str r3, [r2, #0x58]
001a4 e5952004 ldr r2, [r5, #4]
001a8 e5923054 ldr r3, [r2, #0x54]
001ac e3c33303 bic r3, r3, #3, 6
001b0 e5823054 str r3, [r2, #0x54]
001b4 e5952004 ldr r2, [r5, #4]
001b8 e5923058 ldr r3, [r2, #0x58]
001bc e3c33a03 bic r3, r3, #3, 20
001c0 e5823058 str r3, [r2, #0x58]
001c4 e5952004 ldr r2, [r5, #4]
001c8 e5923068 ldr r3, [r2, #0x68]
001cc e3c33803 bic r3, r3, #3, 16
001d0 e5823068 str r3, [r2, #0x68]
001d4 |$L1580|
; 438 :
; 439 : //Garson SSP controller port needs to be configured, Now, we don't have Garson, so, we didn't do this part
; 440 : }
; 441 : return(retval);
001d4 e1a00006 mov r0, r6
; 442 :
; 443 :
; 444 : }
001d8 e8bd41f0 ldmia sp!, {r4 - r8, lr}
001dc e12fff1e bx lr
001e0 |$L1693|
001e0 ffbfdfff DCD 0xffbfdfff
001e4 40901c00 DCD 0x40901c00
001e8 ffcfffbf DCD 0xffcfffbf
001ec 00c0673f DCD 0xc0673f
001f0 |$M1689|
ENDP ; |XllpACodecEnableCodecPcmPath|
EXPORT |XllpACodecDisableCodecPcmPath|
00000 AREA |.text| { |XllpACodecDisableCodecPcmPath| }, CODE, ARM, SELECTION=1 ; comdat noduplicate
00000 AREA |.pdata$$XllpACodecDisableCodecPcmPath|, PDATA, SELECTION=5, ASSOC=|.text| { |XllpACodecDisableCodecPcmPath| } ; comdat associative
|$T1702| DCD |$L1701|
DCD 0x40001001
; Function compile flags: /Ogsy
00000 AREA |.text| { |XllpACodecDisableCodecPcmPath| }, CODE, ARM, SELECTION=1 ; comdat noduplicate
00000 |XllpACodecDisableCodecPcmPath| PROC
; 456 : {
00000 |$L1701|
00000 e92d4010 stmdb sp!, {r4, lr}
00004 |$M1699|
00004 e1a04001 mov r4, r1
; 457 : XLLP_ACODEC_ERROR_T retval=XLLP_ACODEC_SUCCESS;
; 458 :
; 459 : (pDeviceContext->pSSPReg)->sscr0 &=~XLLP_SSCR0_SSE;
00008 e5942014 ldr r2, [r4, #0x14]
; 460 : XllpOstDelayMicroSeconds( pDeviceContext->pOSTRegs,1);
0000c e3a01001 mov r1, #1
00010 e5923000 ldr r3, [r2]
00014 e3c33080 bic r3, r3, #0x80
00018 e5823000 str r3, [r2]
0001c e5940024 ldr r0, [r4, #0x24]
00020 eb000000 bl XllpOstDelayMicroSeconds
; 461 : (pDeviceContext->pClockReg)->cken &=~XLLP_CLKEN_SSP2;
00024 e5942010 ldr r2, [r4, #0x10]
; 462 :
; 463 : return (retval);
00028 e3a00000 mov r0, #0
0002c e5923004 ldr r3, [r2, #4]
00030 e3c33008 bic r3, r3, #8
00034 e5823004 str r3, [r2, #4]
; 464 : }
00038 e8bd4010 ldmia sp!, {r4, lr}
0003c e12fff1e bx lr
00040 |$M1700|
ENDP ; |XllpACodecDisableCodecPcmPath|
END
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