📄 xllp_suspendresumea.lst
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106 00000038
107 00000038 e129f002 msr cpsr, r2 ; restore cpsr - return to previous mode
108 0000003c
109 0000003c e1a00004 mov r0, r4 ; return final address
110 00000040 e8bd40fe ldmia sp!, {r1-r7,lr} ; restore registers we may have used
111 00000044
112 00000044 RETURN
24 00000044 IF :DEF: Interworking
25 00000044 IF Interworking :LOR: Thumbing
26 00000044 e12fff1e bx lr
27 00000048 ELSE
29 00000048 ENDIF ; ELSE of IF Interworking :LOR: Thumbing
30 00000048 ELSE ; IF :DEF: Interworking
32 00000048 ENDIF ; ELSE OF IF :DEF: Interworking
33 00000048
113 00000048 ENDFUNC
114 00000048
115 00000048 ; R0 = pseudo-stack pointer (updated on return)
116 00000048 ; R1 = mode
117 00000048 Xllp_RestoreMSARMRegs FUNCTION
118 00000048 e92d40fe stmdb sp!, {r1-r7,lr} ; Save registers we may use (except r0)
119 0000004c
120 0000004c e1a04000 mov r4, r0 ; setup pseudo stack pointer
121 00000050 e201101f and r1, r1, #(xlli_CPSR_Mode_MASK) ; mode bits only
122 00000054
123 00000054 e10f0000 mrs r0, cpsr
124 00000058 e1a02000 mov r2, r0 ; save cpsr to restore before returning
125 0000005c
126 0000005c e3c0001f bic r0, r0, #(xlli_CPSR_Mode_MASK)
127 00000060 e38000c0 orr r0, r0, #(xlli_CPSR_I_Bit:OR:xlli_CPSR_F_Bit) ; no interrupts
128 00000064 e1800001 orr r0, r0, r1 ; Set requested mode
129 00000068 e129f000 msr cpsr, r0
130 0000006c
131 0000006c e3510011 cmp r1, #xlli_CPSR_Mode_FIQ
132 00000070 08b47f01 ldmeqia r4!, {r0,r8-r12,sp,lr} ; Restore SPSR, r8-r12, SP, LR, for FIQ mode
133 00000074 18b46001 ldmneia r4!, {r0,sp,lr} ; Restore SPSR, SP, LR, for other requested mode
134 00000078 ; SYS mode doesn't have an SPSR
135 00000078 e351001f cmp r1, #xlli_CPSR_Mode_SYS
136 0000007c 1169f000 msrne spsr, r0
137 00000080
138 00000080 e129f002 msr cpsr, r2 ; return to previous mode
139 00000084
140 00000084 e1a00004 mov r0, r4 ; return final address
141 00000088 e8bd40fe ldmia sp!, {r1-r7,lr} ; restore registers we may have used
142 0000008c
143 0000008c RETURN
24 0000008c IF :DEF: Interworking
25 0000008c IF Interworking :LOR: Thumbing
26 0000008c e12fff1e bx lr
27 00000090 ELSE
29 00000090 ENDIF ; ELSE of IF Interworking :LOR: Thumbing
30 00000090 ELSE ; IF :DEF: Interworking
32 00000090 ENDIF ; ELSE OF IF :DEF: Interworking
33 00000090
144 00000090 ENDFUNC
145 00000090
146 00000090 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
147 00000090 ; This function saves the various MMU registers.
148 00000090 ; Restore of the MMU is done in Xllp_ResumePhase2A (which is linked into the boot loaders).
149 00000090 ; r0 = address of MMU save area
150 00000090 Xllp_SaveMMU FUNCTION
151 00000090 e92d40fe stmdb sp!, {r1-r7,lr} ; Save regs we may use
152 00000094
153 00000094 ; Save argument to free up r0
154 00000094 e1a05000 mov r5, r0
155 00000098
156 00000098 ; Cp15_ACR_MMU
157 00000098 ee110f10 mrc p15, 0, r0, c1, c0, 0 ; load r0 with MMU Control
158 0000009c ;ldr r1, =XLLP_CP15_ACR_MMU_VLD_MSK ; mask off the undefined bits
159 0000009c ;and r0, r0, r1
160 0000009c e5850018 str r0, [r5, #RESUMEPHASE2_CP15_ACR_MMU_OFFSET] ; store MMU Control data
161 000000a0
162 000000a0 ; Cp15_AUXCR_MMU; // cp15 Reg1:1: assume restored elsewhere.
163 000000a0 ee110f11 mrc p15, 0, r0, c1, c1, 0 ; load r0 with MMU Aux Control
164 000000a4 ;ldr r1, =XLLP_CP15_AUXCR_MMU_VLD_MSK ; mask off the undefined bits
165 000000a4 ;and r0, r0, r1
166 000000a4 e585001c str r0, [r5, #RESUMEPHASE2_CP15_AUXCR_MMU_OFFSET] ; store MMU Aux Control data
167 000000a8
168 000000a8 ; Cp15_TTBR_MMU; // cp15 Reg2:0
169 000000a8 ee120f10 mrc p15, 0, r0, c2, c0, 0 ; load r0 with TTB address.
170 000000ac ;ldr r1, =XLLP_CP15_TTBR_MMU_VLD_MSK ; mask off the undefined bits
171 000000ac ;and r0, r0, r1
172 000000ac e5850020 str r0, [r5, #RESUMEPHASE2_CP15_TTBR_MMU_OFFSET] ; store TTB address
173 000000b0
174 000000b0 ; Cp15_DACR_MMU; // cp15 Reg3:0, all bits valid
175 000000b0 ee130f10 mrc p15, 0, r0, c3, c0, 0 ; load r0 with domain access control.
176 000000b4 e5850024 str r0, [r5, #RESUMEPHASE2_CP15_DACR_MMU_OFFSET] ; store domain access control
177 000000b8
178 000000b8 ; Cp15_PID_MMU; // cp15 Reg13; Assume set by OS if used.
179 000000b8 ee1d0f10 mrc p15, 0, r0, c13, c0, 0 ; load r0 with PID.
180 000000bc ;ldr r1, =XLLP_CP15_PID_MMU_VLD_MSK ; mask off the undefined bits
181 000000bc ;and r0, r0, r1
182 000000bc e5850028 str r0, [r5, #RESUMEPHASE2_CP15_PID_MMU_OFFSET] ; store PID
183 000000c0
184 000000c0 e8bd40fe ldmia sp!, {r1-r7,lr} ; Restore regs we may have used
185 000000c4 RETURN
24 000000c4 IF :DEF: Interworking
25 000000c4 IF Interworking :LOR: Thumbing
26 000000c4 e12fff1e bx lr
27 000000c8 ELSE
29 000000c8 ENDIF ; ELSE of IF Interworking :LOR: Thumbing
30 000000c8 ELSE ; IF :DEF: Interworking
32 000000c8 ENDIF ; ELSE OF IF :DEF: Interworking
33 000000c8
186 000000c8
187 000000c8 ENDFUNC
188 000000c8
189 000000c8 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
190 000000c8 ; This is the function that actually powers the system off.
191 000000c8 ; r0 = address of suspend save area
192 000000c8 Xllp_SuspendAndResumeA FUNCTION
193 000000c8 ; Save current mode registers on the current mode stack.
194 000000c8 e92d5fff stmdb sp!, {r0-r12,lr}
195 000000cc
196 000000cc ; Move parameter to free up r0
197 000000cc e1a05000 mov r5, r0
198 000000d0
199 000000d0 ; Save the SP
200 000000d0 ; This is the value that should be restored on resume before jumping to XllpResume below
201 000000d0 e585d008 str sp, [r5, #RESUMEPHASE2_SP_OFFSET]
202 000000d4
203 000000d4 ; Save CPSR
204 000000d4 e10f3000 mrs r3, cpsr
205 000000d8 e585300c str r3, [r5, #RESUMEPHASE2_CPSR_OFFSET]
206 000000dc
207 000000dc ; Save Coprocessor Access Register
208 000000dc ee1f0f11 mrc p15, 0, r0, c15, c1, 0
209 000000e0 e5850010 str r0, [r5, #RESUMEPHASE2_CPAR_OFFSET]
210 000000e4
211 000000e4 ; Save the resume address
212 000000e4 e28f0078 add r0, pc, #XllpResumePhase3 - (. + 8)
213 000000e8 e5850014 str r0, [r5, #RESUMEPHASE2_RESUMEPHASE3_PC_OFFSET]
214 000000ec
215 000000ec ; Save the MMU
216 000000ec e1a00005 mov r0, r5
217 000000f0 ebffffe6 bl Xllp_SaveMMU
218 000000f4
219 000000f4 ; Store word and checksum (word count is included in checksum)
220 000000f4 e3a0100b mov r1, #RESUMEPHASE2_DATA_WORDS
221 000000f8 e5851004 str r1, [r5, #RESUMEPHASE2_WORDCOUNT_OFFSET]
222 000000fc e2850004 add r0, r5, #RESUMEPHASE2_WORDCOUNT_OFFSET
223 00000100 eb000000 bl Xllp_SimpleChecksum
224 00000104 e5850000 str r0, [r5, #RESUMEPHASE2_CHECKSUM_OFFSET]
225 00000108
226 00000108 ; At this point all state has been saved.
227 00000108 ; The cache and write buffers need to be flushed before power down.
228 00000108 ; Cache flushing is OS dependent, so OSD_CacheFlush needs to be provided for each OS environment.
229 00000108 ; It must simply ensure that all cached and buffered data has been written back to memory.
230 00000108 e92d4000 stmdb sp!, {lr}
231 0000010c eb000000 bl OSD_CacheFlush
232 00000110 e8bd4000 ldmia sp!, {lr}
233 00000114 e1a00000 nop
234 00000118 e1a00000 nop
235 0000011c e1a00000 nop
236 00000120 e1a00000 nop
237 00000124
238 00000124 ;================================================================
239 00000124 XllpEnterSleepMode
240 00000124 ;================================================================
241 00000124 e3a03003 ldr r3, =(xlli_PWRMODE_SLEEP)
242 00000128 ea000004 b %F1 ; Purely precautionary, in case we needed to clear pipeline
243 0000012c 00 00 00 ALIGN 32
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00
244 00000140 1
245 00000140 ee073e10 mcr p14, 0, r3, c7, c0, 0 ; Enter sleep
246 00000144
247 00000144 e1a00000 nop
248 00000148 e1a00000 nop
249 0000014c e1a00000 nop
250 00000150 e1a00000 nop
251 00000154 e1a00000 nop
252 00000158 e1a00000 nop
253 0000015c e1a00000 nop
254 00000160 e1a00000 nop
255 00000164 ;================================================================
256 00000164 XllpResumePhase3
257 00000164 ;================================================================
258 00000164 ; This is where we should end up here when we resume.
259 00000164 ; The MMU, CPU mode, and stack should have been restored at this point so
260 00000164 ; adrresses should be virtual and the stack should look as it did when we saved the SP above
261 00000164 ; All that remains to be done here is to restore the current mode registers.
262 00000164 e8bd5fff ldmia sp!, {r0-r12,lr}
263 00000168 RETURN
24 00000168 IF :DEF: Interworking
25 00000168 IF Interworking :LOR: Thumbing
26 00000168 e12fff1e bx lr
27 0000016c ELSE
29 0000016c ENDIF ; ELSE of IF Interworking :LOR: Thumbing
30 0000016c ELSE ; IF :DEF: Interworking
32 0000016c ENDIF ; ELSE OF IF :DEF: Interworking
33 0000016c
264 0000016c ENDFUNC
265 0000016c ;**************************************************************************************************
266 0000016c END
Assembly terminated, errors: 0, warnings: 0
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