📄 xllp_suspendresumea.lst
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279 00000000 xlli_OWER_offset EQU (0x18) ; OS Timer Watchdog Enable Register
280 00000000 xlli_OIER_offset EQU (0x1C) ; OS Timer Interrupt Enable Register
281 00000000
282 00000000 xlli_OSCR4_offset EQU (0x40) ; OS Timer Count Register 4
283 00000000 xlli_OSCR5_offset EQU (0x44) ; OS Timer Count Register 5
284 00000000 xlli_OSCR6_offset EQU (0x48) ; OS Timer Count Register 6
285 00000000 xlli_OSCR7_offset EQU (0x4C) ; OS Timer Count Register 7
286 00000000 xlli_OSCR8_offset EQU (0x50) ; OS Timer Count Register 8
287 00000000 xlli_OSCR9_offset EQU (0x54) ; OS Timer Count Register 9
288 00000000 xlli_OSCR10_offset EQU (0x58) ; OS Timer Count Register 10
289 00000000 xlli_OSCR11_offset EQU (0x5C) ; OS Timer Count Register 11
290 00000000
291 00000000 xlli_OSMR4_offset EQU (0x80) ; OS Timer Match Register 4
292 00000000 xlli_OSMR5_offset EQU (0x84) ; OS Timer Match Register 5
293 00000000 xlli_OSMR6_offset EQU (0x88) ; OS Timer Match Register 6
294 00000000 xlli_OSMR7_offset EQU (0x8C) ; OS Timer Match Register 7
295 00000000 xlli_OSMR8_offset EQU (0x90) ; OS Timer Match Register 8
296 00000000 xlli_OSMR9_offset EQU (0x94) ; OS Timer Match Register 9
297 00000000 xlli_OSMR10_offset EQU (0x98) ; OS Timer Match Register 10
298 00000000 xlli_OSMR11_offset EQU (0x9C) ; OS Timer Match Register 11
299 00000000
300 00000000 xlli_OMCR4_offset EQU (0xC0) ; OS Timer Match Control Register 4
301 00000000 xlli_OMCR5_offset EQU (0xC4) ; OS Timer Match Control Register 5
302 00000000 xlli_OMCR6_offset EQU (0xC8) ; OS Timer Match Control Register 6
303 00000000 xlli_OMCR7_offset EQU (0xCC) ; OS Timer Match Control Register 7
304 00000000 xlli_OMCR8_offset EQU (0xD0) ; OS Timer Match Control Register 8
305 00000000 xlli_OMCR9_offset EQU (0xD4) ; OS Timer Match Control Register 9
306 00000000 xlli_OMCR10_offset EQU (0xD8) ; OS Timer Match Control Register 10
307 00000000 xlli_OMCR11_offset EQU (0xDC) ; OS Timer Match Control Register 11
308 00000000
309 00000000 xlli_OSSR_ALL EQU (0xFFF) ; Match register status "sticky bits"
310 00000000 xlli_OIER_E1 EQU (0x002) ; Interrupt enable bit for match register #1
311 00000000
312 00000000 ;
313 00000000 ; REAL TIME CLOCK (RTC) REGISTERS base address and register offsets from the base address
314 00000000 ;
315 00000000
316 00000000 xlli_RTCREGS_PHYSICAL_BASE EQU (0x40900000)
317 00000000
318 00000000 xlli_RCNR_offset EQU (0x00) ; RTC Counter Register
319 00000000 xlli_RTAR_offset EQU (0x04) ; RTC Alarm Register
320 00000000 xlli_RTSR_offset EQU (0x08) ; RTC Status Register
321 00000000 xlli_RTTR_offset EQU (0x0C) ; RTC Timer Trim Register
322 00000000 xlli_RDCR_offset EQU (0x10) ; RTC Day Counter Register
323 00000000 xlli_RYCR_offset EQU (0x14) ; RTC Year Counter Register
324 00000000 xlli_RDAR1_offset EQU (0x18) ; RTC Day Alarm Register 1
325 00000000 xlli_RYAR1_offset EQU (0x1C) ; RTC Year Alarm Register 2
326 00000000 xlli_RDAR2_offset EQU (0x20) ; RTC Day Alarm Register 2
327 00000000 xlli_RYAR2_offset EQU (0x24) ; RTC Year Alarm Register 2
328 00000000 xlli_SWCR_offset EQU (0x28) ; Stopwatch Counter Register
329 00000000 xlli_SWAR1_offset EQU (0x2C) ; Stopwatch Alarm Register 1
330 00000000 xlli_SWAR2_offset EQU (0x30) ; Stopwatch Alarm Register 2
331 00000000 xlli_PICR_offset EQU (0x34) ; Periodic Interrupt Counter Register
332 00000000 xlli_PIAR_offset EQU (0x38) ; Periodic Interrupt Alarm Register
333 00000000
334 00000000
335 00000000 ; Oscillator Controller bit defs
336 00000000
337 00000000 xlli_OSCC_OOK EQU (0x01) ; Oscillator OK bit
338 00000000 xlli_OSCC_OON EQU (0x02) ; Timekeeping (32.768KHz) Osc bit
339 00000000 xlli_OSCC_TOUT_EN EQU (0x04) ; Timekeeping Output enable
340 00000000 xlli_OSCC_PIO_EN EQU (0x08) ; Processor Oscillator Output Enable
341 00000000 xlli_OSCC_CRI EQU (0x10) ; Processor Oscillator Output Enable
342 00000000
343 00000000 ;
344 00000000 ; Coprocessor 15 data bits
345 00000000 ;
346 00000000
347 00000000 xlli_control_icache EQU (0x1000) ; bit 12 - i-cache bit
348 00000000 xlli_control_btb EQU (0x0800) ; bit 11 - btb bit
349 00000000 xlli_control_r EQU (0x0200) ; Bit 9
350 00000000 xlli_control_s EQU (0x0100) ; Bit 8
351 00000000 xlli_control_dcache EQU (0x0004) ; Bit 2 - d-cache bit
352 00000000 xlli_control_mmu EQU (0x0001) ; Bit 0 - MMU bit
353 00000000
354 00000000
355 00000000 ;
356 00000000 ; CP 15 related settings
357 00000000 ;
358 00000000
359 00000000 xlli_PID EQU (0x00)
360 00000000 xlli_DACR EQU (0x01)
361 00000000 xlli_CONTROL_DCACHE EQU (0x04)
362 00000000 xlli_CONTROL_MINIDATA_01 EQU (0x10)
363 00000000 xlli_CONTROL_BTB EQU (0x800) ; Brach Target Buffer bit
364 00000000
365 00000000 ;
366 00000000 ; register bit masks - RCSR
367 00000000 ;
368 00000000 xlli_RCSR_HWR EQU (0x01)
369 00000000 xlli_RCSR_WDR EQU (0x02)
370 00000000 xlli_RCSR_SMR EQU (0x04)
371 00000000 xlli_RCSR_GPR EQU (0x08)
372 00000000 xlli_RCSR_ALL EQU (0xF)
373 00000000
374 00000000
375 00000000 ;
376 00000000 ; CPSR Processor constants
377 00000000
378 00000000 xlli_CPSR_Mode_MASK EQU (0x0000001F)
379 00000000 xlli_CPSR_Mode_USR EQU (0x10)
380 00000000 xlli_CPSR_Mode_FIQ EQU (0x11)
381 00000000 xlli_CPSR_Mode_IRQ EQU (0x12)
382 00000000 xlli_CPSR_Mode_SVC EQU (0x13)
383 00000000 xlli_CPSR_Mode_ABT EQU (0x17)
384 00000000 xlli_CPSR_Mode_UND EQU (0x1B)
385 00000000 xlli_CPSR_Mode_SYS EQU (0x1F)
386 00000000
387 00000000 xlli_CPSR_I_Bit EQU (0x80)
388 00000000 xlli_CPSR_F_Bit EQU (0x40)
389 00000000
390 00000000
391 00000000 xlli_PWRMODE_SLEEP EQU (0x00000003) ; Value for cp14: Reg7 to induce sleep.
392 00000000 ; Bit settings
393 00000000 ;
394 00000000 xlli_BIT_0 EQU 0x00000001
395 00000000 xlli_BIT_1 EQU 0x00000002
396 00000000 xlli_BIT_2 EQU 0x00000004
397 00000000 xlli_BIT_3 EQU 0x00000008
398 00000000 xlli_BIT_4 EQU 0x00000010
399 00000000 xlli_BIT_5 EQU 0x00000020
400 00000000 xlli_BIT_6 EQU 0x00000040
401 00000000 xlli_BIT_7 EQU 0x00000080
402 00000000 xlli_BIT_8 EQU 0x00000100
403 00000000 xlli_BIT_9 EQU 0x00000200
404 00000000 xlli_BIT_10 EQU 0x00000400
405 00000000 xlli_BIT_11 EQU 0x00000800
406 00000000 xlli_BIT_12 EQU 0x00001000
407 00000000 xlli_BIT_13 EQU 0x00002000
408 00000000 xlli_BIT_14 EQU 0x00004000
409 00000000 xlli_BIT_15 EQU 0x00008000
410 00000000 xlli_BIT_16 EQU 0x00010000
411 00000000 xlli_BIT_17 EQU 0x00020000
412 00000000 xlli_BIT_18 EQU 0x00040000
413 00000000 xlli_BIT_19 EQU 0x00080000
414 00000000 xlli_BIT_20 EQU 0x00100000
415 00000000 xlli_BIT_21 EQU 0x00200000
416 00000000 xlli_BIT_22 EQU 0x00400000
417 00000000 xlli_BIT_23 EQU 0x00800000
418 00000000 xlli_BIT_24 EQU 0x01000000
419 00000000 xlli_BIT_25 EQU 0x02000000
420 00000000 xlli_BIT_26 EQU 0x04000000
421 00000000 xlli_BIT_27 EQU 0x08000000
422 00000000 xlli_BIT_28 EQU 0x10000000
423 00000000 xlli_BIT_29 EQU 0x20000000
424 00000000 xlli_BIT_30 EQU 0x40000000
425 00000000 xlli_BIT_31 EQU 0x80000000
426 00000000 END
50 00000000 ;
51 AREA |.text|, CODE, READONLY, ALIGN=5 ; Align =5 required for "ALIGN 32" to work
52 00000000 ;
53 00000000 ; Functions made public by this file:
54 00000000 ;
55 00000000 EXPORT Xllp_SuspendAndResumeA
56 00000000 EXPORT Xllp_SaveMMU
57 00000000 EXPORT Xllp_SaveMSARMRegs
58 00000000 EXPORT Xllp_RestoreMSARMRegs
59 00000000
60 00000000 ; External functions we need
61 00000000 IMPORT Xllp_SimpleChecksum
62 00000000 IMPORT OSD_CacheFlush
63 00000000
64 00000000 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
65 00000000 ; Xllp_SaveMSARMRegs and Xllp_RestoreMSARMRegs
66 00000000 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
67 00000000 ; Mode specific (MS) ARM registers are are saved and restored by the following functions.
68 00000000 ; For all modes other than FIQ mode, 'mode specific' means SP, LR, and SPSR.
69 00000000 ; R8-R12 are specific to FIQ mode but are common to all other modes.
70 00000000 ; This is described in the ARM Architecture Reference Manual.
71 00000000 ;
72 00000000 ; Registers common to all modes are not saved and restored by these functions.
73 00000000 ; It is left to the calling routine to save and restore the common registers.
74 00000000 ;
75 00000000 ; A 'pseudo-stack' is used to save the registers.
76 00000000 ; The term 'pseudo-stack' is used because the customary stmdb and ldmia register saving instructions are used.
77 00000000 ; However, since SP itself is mode specific, the current stack is not used.
78 00000000 ; Previous counterparts of this code used the current stack for each mode as the save area.
79 00000000 ; The approach used here means that we don't care what modes actually have their SP setup.
80 00000000 ; All that matters is that the current mode stack is valid.
81 00000000 ; This approach is likely to work with different operating systems regardless of what modes they use.
82 00000000 ;
83 00000000
84 00000000 ; R0 = pseudo-stack pointer (updated on return)
85 00000000 ; R1 = mode
86 00000000 Xllp_SaveMSARMRegs FUNCTION
87 00000000 e92d40fe stmdb sp!, {r1-r7,lr} ; Save registers we may use (except r0)
88 00000004
89 00000004 e1a04000 mov r4, r0 ; setup pseudo stack pointer
90 00000008 e201101f and r1, r1, #(xlli_CPSR_Mode_MASK) ; get mode only
91 0000000c
92 0000000c e10f0000 mrs r0, cpsr
93 00000010 e1a02000 mov r2, r0 ; save cpsr to restore before returning
94 00000014
95 00000014 e3c0001f bic r0, r0, #(xlli_CPSR_Mode_MASK)
96 00000018 e38000c0 orr r0, r0, #(xlli_CPSR_I_Bit:OR:xlli_CPSR_F_Bit) ; no interrupts
97 0000001c e1800001 orr r0, r0, r1 ; Set requested mode
98 00000020 e129f000 msr cpsr, r0
99 00000024
100 00000024 ; SYS mode doesn't have an SPSR
101 00000024 e351001f cmp r1, #xlli_CPSR_Mode_SYS
102 00000028 114f0000 mrsne r0, spsr
103 0000002c e3510011 cmp r1, #xlli_CPSR_Mode_FIQ
104 00000030 09247f01 stmeqdb r4!, {r0,r8-r12,sp,lr} ; Save SPSR, r8-r12, SP, LR, for FIQ mode
105 00000034 19246001 stmnedb r4!, {r0,sp,lr} ; Save SPSR, SP, LR, for other requested mode
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