📄 xllp_suspendresumea.lst
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75 00000000 xlli_GPCR1_offset EQU (0x028)
76 00000000 xlli_GPCR2_offset EQU (0x02C)
77 00000000 xlli_GPCR3_offset EQU (0x124)
78 00000000
79 00000000 xlli_GAFR0_L_offset EQU (0x054) ; GPIO Alternate function registers (Bits 15:0)
80 00000000 xlli_GAFR0_U_offset EQU (0x058) ; Bits 31:16
81 00000000 xlli_GAFR1_L_offset EQU (0x05c) ; Bits 47:32
82 00000000 xlli_GAFR1_U_offset EQU (0x060) ; Bits 63:48
83 00000000 xlli_GAFR2_L_offset EQU (0x064) ; Bits 79:64
84 00000000 xlli_GAFR2_U_offset EQU (0x068) ; Bits 95:80
85 00000000 xlli_GAFR3_L_offset EQU (0x06C) ; Bits 111:96
86 00000000 xlli_GAFR3_U_offset EQU (0x070) ; Bits 127:112
87 00000000
88 00000000 ;
89 00000000 ; POWER MANAGER base address and register offsets from the base address
90 00000000 ;
91 00000000
92 00000000 xlli_PMRCREGS_PHYSICAL_BASE EQU 0x40F00000
93 00000000
94 00000000 xlli_PMCR_offset EQU (0x00) ; Power Manager Control Register
95 00000000 xlli_PSSR_offset EQU (0x04) ; Power Manager Sleep Status Register
96 00000000 xlli_PSPR_offset EQU (0x08) ; Power Manager Scratch Pad Register
97 00000000 xlli_PWER_offset EQU (0x0C) ; Power Manager Wake-up Enable Register
98 00000000 xlli_PRER_offset EQU (0x10) ; Power Manager GPIO Rising-edge Detect Enable Register
99 00000000 xlli_PFER_offset EQU (0x14) ; Power Manager GPIO Falling-edge Detect Enable Register
100 00000000 xlli_PEDR_offset EQU (0x18) ; Power Manager GPIO Edge Detect Status Register
101 00000000 xlli_PCFR_offset EQU (0x1C) ; Power Manager General Configuration Register
102 00000000 xlli_PGSR0_offset EQU (0x20) ; Power Manager GPIO Sleep State Register for GP [31-0]
103 00000000 xlli_PGSR1_offset EQU (0x24) ; Power Manager GPIO Sleep State Register for GP [63-32]
104 00000000 xlli_PGSR2_offset EQU (0x28) ; Power Manager GPIO Sleep State Register for GP [95-64]
105 00000000 xlli_PGSR3_offset EQU (0x2C) ; Power Manager GPIO Sleep State Register for GP [120-96]
106 00000000 xlli_RCSR_offset EQU (0x30) ; Reset Controller Status Register
107 00000000 xlli_PSLR_offset EQU (0x34) ; Power Manager Sleep Mode Config Register
108 00000000 xlli_PSTR_offset EQU (0x38) ; Power Manager Standby Mode Config Register
109 00000000 xlli_PSNR_offset EQU (0x3C) ; Power Manager Sense Moce Config Register
110 00000000 xlli_PVCR_offset EQU (0x40) ; Power Manager Voltage Change Control Register
111 00000000 xlli_PKWR_offset EQU (0x50) ; Power Manager Keyboard Wake-up Enable Register
112 00000000 xlli_PKSR_offset EQU (0x54) ; Power Manager Keyboard Edge-Detect Status Register
113 00000000 xlli_PI2DBR_offset EQU (0x188) ; Power I2C Data Buffer Register
114 00000000 xlli_PI2CR_offset EQU (0x190) ; Power I2C Control Register
115 00000000 xlli_PI2SR_offset EQU (0x198) ; Power I2C Status Register
116 00000000 xlli_PI2SAR_offset EQU (0x1A0) ; Power I2C Slave Address Register
117 00000000
118 00000000 ;
119 00000000 ; POWER MANAGER register bit masks
120 00000000 ;
121 00000000 xlli_PSSR_SSS EQU (0x01) ; Software Sleep Status
122 00000000 xlli_PSSR_BFS EQU (0x02) ; Battery Fault Status
123 00000000 xlli_PSSR_VFS EQU (0x04) ; VCC Fault Status
124 00000000 xlli_PSSR_PH EQU (0x10) ; Peripheral Control Hold
125 00000000 xlli_PSSR_RDH EQU (0x20) ; Read Disable Hold
126 00000000
127 00000000 xlli_PCFR_OPDE EQU (0x01) ; Processor (13MHz) osc power-down enable
128 00000000 xlli_PCFR_FP EQU (0x02) ; Float PCMCIA during sleep modes
129 00000000 xlli_PCFR_FS EQU (0x04) ; Float Static Chip Selects
130 00000000 xlli_PCFR_GPR_EN EQU (0x10) ; GPIO 1 performs GPIO reset
131 00000000 xlli_PCFR_SYSEN_EN EQU (0x20) ; SYS_EN pin
132 00000000 xlli_PCFR_PI2C_EN EQU (0x40) ;
133 00000000 xlli_PCFR_DC_EN EQU (0x80) ; Deep-Sleep Mode
134 00000000 xlli_PCFR_FVC EQU (0x400) ;
135 00000000 xlli_PCFR_L1_EN EQU (0x800) ;
136 00000000 xlli_PCFR_GPROD EQU (0x1000) ;
137 00000000 xlli_PCFR_PO EQU (0x4000) ;
138 00000000 xlli_PCFR_RO EQU (0x8000) ;
139 00000000 xlli_PCFR_USEDBITS EQU (xlli_PCFR_OPDE :OR: xlli_PCFR_FP :OR: xlli_PCFR_FS :OR: xlli_PCFR_GPR_EN :OR:
xlli_PCFR_SYSEN_EN :OR: xlli_PCFR_PI2C_EN :OR: xlli_PCFR_DC_EN :OR: xlli_PCFR_FVC :OR:
xlli_PCFR_L1_EN :OR: xlli_PCFR_GPROD :OR: xlli_PCFR_PO :OR: xlli_PCFR_RO)
142 00000000
143 00000000 xlli_PWER_WE0 EQU (0x01) ; Wake-up Enable GPIO pin 0
144 00000000 xlli_PWER_WE1 EQU (0x02) ; Wake-up Enable GPIO pin 1
145 00000000 xlli_PWER_WERTC EQU (0x80000000) ; RTC Standby, Wake-up Enable-
146 00000000
147 00000000 ;
148 00000000 ; MEMORY CONTROLLER base address and register offsets from the base address
149 00000000 ;
150 00000000
151 00000000 xlli_MEMORY_CONFIG_BASE EQU 0x48000000
152 00000000
153 00000000 xlli_MDCNFG_offset EQU (0x00)
154 00000000 xlli_MDREFR_offset EQU (0x04)
155 00000000 xlli_MSC0_offset EQU (0x08)
156 00000000 xlli_MSC1_offset EQU (0x0C)
157 00000000 xlli_MSC2_offset EQU (0x10)
158 00000000 xlli_MECR_offset EQU (0x14)
159 00000000 xlli_SXLCR_offset EQU (0x18)
160 00000000 xlli_SXCNFG_offset EQU (0x1C)
161 00000000 xlli_FLYCNFG_offset EQU (0x20)
162 00000000 xlli_SXMRS_offset EQU (0x24)
163 00000000 xlli_MCMEM0_offset EQU (0x28)
164 00000000 xlli_MCMEM1_offset EQU (0x2C)
165 00000000 xlli_MCATT0_offset EQU (0x30)
166 00000000 xlli_MCATT1_offset EQU (0x34)
167 00000000 xlli_MCIO0_offset EQU (0x38)
168 00000000 xlli_MCIO1_offset EQU (0x3C)
169 00000000 xlli_MDMRS_offset EQU (0x40)
170 00000000 xlli_BOOT_DEF_offset EQU (0x44)
171 00000000 xlli_ARB_CNTL_offset EQU (0x48)
172 00000000 xlli_BSCNTR0_offset EQU (0x4C)
173 00000000 xlli_BSCNTR1_offset EQU (0x50)
174 00000000 xlli_LCDBSCNTR_offset EQU (0x54)
175 00000000 xlli_MDMRSLP_offset EQU (0x58)
176 00000000 xlli_BSCNTR2_offset EQU (0x5C)
177 00000000 xlli_BSCNTR3_offset EQU (0x60)
178 00000000
179 00000000 ; Memory Controller bit defs
180 00000000
181 00000000 xlli_MDREFR_K0DB4 EQU (0x20000000) ; Sync Static Clock 0 divide by 4 control/status
182 00000000 xlli_MDREFR_K2FREE EQU (0x02000000) ; Set to force SDCLK[2] to be free running
183 00000000 xlli_MDREFR_K1FREE EQU (0x01000000) ; Set to force SDCLK[1] to be free running
184 00000000 xlli_MDREFR_K0FREE EQU (0x00800000) ; Set to force SDCLK[0] to be free running
185 00000000 xlli_MDREFR_SLFRSH EQU (0x00400000) ; Self Refresh Control Status bit
186 00000000 xlli_MDREFR_APD EQU (0x00100000) ; Auto Power Down bit
187 00000000 xlli_MDREFR_K2DB2 EQU (0x00080000) ; SDRAM clock pin 2 divide by 2 control/status
188 00000000 xlli_MDREFR_K1DB2 EQU (0x00020000) ; SDRAM clock pin 1 divide by 2 control/status
189 00000000 xlli_MDREFR_K1RUN EQU (0x00010000) ; SDRAM clock pin 1 run/control status
190 00000000 xlli_MDREFR_E1PIN EQU (0x00008000) ; SDRAM clock Enable pin 1 level control/status
191 00000000 xlli_MDREFR_K0DB2 EQU (0x00004000) ; Sync Static Memory Clock divide by 2 control/status
192 00000000 xlli_MDREFR_K0RUN EQU (0x00002000) ; Sync Static Memory Clock Pin 0
193 00000000 xlli_MDREFR_E0PIN EQU (0x00000100) ; SDRAM clock enable pin 0 (Cotulla ONLY!!)
194 00000000
195 00000000 xlli_MDCNFG_DE0 EQU (0x00000001) ; SDRAM enable bit for partition 0
196 00000000 xlli_MDCNFG_DE1 EQU (0x00000002) ; SDRAM enable bit for partition 1
197 00000000 xlli_MDCNFG_DE2 EQU (0x00010000) ; SDRAM enable bit for partition 2
198 00000000 xlli_MDCNFG_DE3 EQU (0x00020000) ; SDRAM enable bit for partition 3
199 00000000 xlli_MDCNFG_DWID0 EQU (0x00000004) ; SDRAM bus width (clear = 32 bits, set = 16 bits)
200 00000000
201 00000000 ;
202 00000000 ; INTERNAL MEMORY CONTROLLER base address and register offsets from the base address
203 00000000 ;
204 00000000
205 00000000 xlli_IMEMORY_CONFIG_BASE EQU (0x58000000)
206 00000000
207 00000000 xlli_IMPMCR_offset EQU (0x00) ; Internal Memory Power Manager Control Register
208 00000000 xlli_IMPMSR_offset EQU (0x08) ; Internal Memory Power Management Status Register
209 00000000
210 00000000
211 00000000 ;
212 00000000 ; UART Definitions
213 00000000 ;
214 00000000 xlli_perif_base EQU (0x40000000) ; Base address of the peripherals
215 00000000 xlli_ffuart_offset EQU (0x00100000) ; Offset to the Full-Feature UART in the peripheral block
216 00000000 xlli_btuart_offset EQU (0x00200000) ; Offset to the BlueTooth UART in the peripheral block
217 00000000 xlli_stuart_offset EQU (0x00700000) ; Offset to the Standard UART in the peripheral block
218 00000000
219 00000000
220 00000000 xlli_uart_thr_offset EQU (0x0) ;DLAB = 0 WO 8bit - Transmit Holding Register
221 00000000 xlli_uart_rbr_offset EQU (0x0) ;DLAB = 0 RO 8bit - Recieve Buffer Register
222 00000000 xlli_uart_dll_offset EQU (0x0) ;DLAB = 1 RW 8bit - Divisor Latch Low Register
223 00000000 xlli_uart_ier_offset EQU (0x4) ;DLAB = 0 RW 8bit - Interrupt Enable Register
224 00000000 xlli_uart_dlh_offset EQU (0x4) ;DLAB = 1 RW 8bit - Divisor Latch High Register
225 00000000 xlli_uart_iir_offset EQU (0x8) ;DLAB = X RO 8bit - Interrupt Identification Register
226 00000000 xlli_uart_fcr_offset EQU (0x8) ;DLAB = X WO 8bit - FIFO Control Register
227 00000000 xlli_uart_lcr_offset EQU (0xC) ;DLAB = X RW 8bit - Line Control Register
228 00000000 xlli_uart_mcr_offset EQU (0x10) ;DLAB = X RW 8bit - Modem Control Regiser
229 00000000 xlli_uart_lsr_offset EQU (0x14) ;DLAB = X RO 8bit - Line Status Register
230 00000000 xlli_uart_msr_offset EQU (0x18) ;DLAB = X RO 8bit - Modem Status Register
231 00000000 xlli_uart_spr_offset EQU (0x1C) ;DLAB = X RW 8bit - Scratchpad Register
232 00000000 xlli_uart_isr_offset EQU (0x20) ;DLAB = X RW 8bit - Slow Infrared Select Register
233 00000000 xlli_uart_for_offset EQU (0x24) ;DLAB = X RO FIFO Occupancy Register
234 00000000 xlli_uart_abr_offset EQU (0x28) ;DLAB = X RW Autobaud Control Register
235 00000000 xlli_uart_acr_offset EQU (0x2C) ;DLAB = X Autobaud Count Register
236 00000000
237 00000000 ;
238 00000000 ; INTERRUPT CONTROLLER base address and register offsets from the base address
239 00000000 ;
240 00000000
241 00000000 xlli_INTERREGS_PHYSICAL_BASE EQU (0x40D00000)
242 00000000
243 00000000 xlli_ICIP_offset EQU (0x00) ; Interrupt Controller IRQ Pending Register
244 00000000 xlli_ICMR_offset EQU (0x04) ; Interrupt Controller Mask Register
245 00000000 xlli_ICLR_offset EQU (0x08) ; Interrupt Controller Level Register
246 00000000 xlli_ICFP_offset EQU (0x0C) ; Interrupt Controller FIQ pending Register
247 00000000 xlli_ICPR_offset EQU (0x10) ; Interrupt Controller Pending Register
248 00000000 xlli_ICCR_offset EQU (0x14) ; Interrupt Controller Control Register
249 00000000 xlli_ICHP_offset EQU (0x18) ; Interrupt Controller Highest Priority Reg
250 00000000 xlli_ICMR2_offset EQU (0xA0) ; Interrupt Controller Mask Register 2
251 00000000 xlli_ICLR2_offset EQU (0xA4) ; Interrupt Controller Level Register 2
252 00000000 xlli_ICCR2_offset EQU (0xAC) ; Interrupt Controller Control Register 2
253 00000000
254 00000000 ;
255 00000000 ; CLOCK REGISTERS base address and register offsets from the base address
256 00000000 ;
257 00000000
258 00000000 xlli_CLKREGS_PHYSICAL_BASE EQU (0x41300000)
259 00000000
260 00000000 xlli_CCCR_offset EQU (0x00) ; Core Clock Configuration Register
261 00000000 xlli_CKEN_offset EQU (0x04) ; Clock-Enable Register
262 00000000 xlli_OSCC_offset EQU (0x08) ; Oscillator Configuration Register
263 00000000 xlli_CCSR_offset EQU (0x0C) ; Core Clock Status Register
264 00000000
265 00000000 xlli_CCCR_A_Bit_Mask EQU (0x1 << 25) ; "A" bit is bit 25 in CCCR
266 00000000 ;
267 00000000 ; OS TIMER REGISTERS base address and register offsets from the base address
268 00000000 ;
269 00000000
270 00000000 xlli_OSTREGS_PHYSICAL_BASE EQU (0x40A00000)
271 00000000
272 00000000 xlli_OSMR0_offset EQU (0x00) ; OS Timer Match Register 0
273 00000000 xlli_OSMR1_offset EQU (0x04) ; OS Timer Match Register 1
274 00000000 xlli_OSMR2_offset EQU (0x08) ; OS Timer Match Register 2
275 00000000 xlli_OSMR3_offset EQU (0x0C) ; OS Timer Match Register 3
276 00000000
277 00000000 xlli_OSCR0_offset EQU (0x10) ; OS Timer Count Register 0
278 00000000 xlli_OSSR_offset EQU (0x14) ; OS Timer Status Register
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