📄 xllp_suspendresumea.lst
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ARM macroassembler Page:1
1 00000000 ;******************************************************************************
2 00000000 ;
3 00000000 ; COPYRIGHT (C) 2002-2005 Intel Corporation.
4 00000000 ;
5 00000000 ; This software as well as the software described in it is furnished under
6 00000000 ; license and may only be used or copied in accordance with the terms of the
7 00000000 ; license. The information in this file is furnished for informational use
8 00000000 ; only, is subject to change without notice, and should not be construed as
9 00000000 ; a commitment by Intel Corporation. Intel Corporation assumes no
10 00000000 ; responsibility or liability for any errors or inaccuracies that may appear
11 00000000 ; in this document or any software that may be provided in association with
12 00000000 ; this document.
13 00000000 ;
14 00000000 ; Except as permitted by such license, no part of this document may be
15 00000000 ; reproduced, stored in a retrieval system, or transmitted in any form or by
16 00000000 ; any means without the express written consent of Intel Corporation.
17 00000000 ;
18 00000000 ;******************************************************************************
19 00000000 ; PURPOSE:
20 00000000 ; Suspend/Resume functions linked into the OS kernel.
21 00000000 ;
22 00000000 ; NOTES:
23 00000000 ;
24 00000000 ; Conext:
25 00000000 ; These functions assume that the MMU is enabled, the stack is valid, and CPU is in a priveledged mode.
26 00000000 ; These functions are linked into the OS kernel. They are not linked into the boot loaders.
27 00000000 ;
28 00000000 ; Resume phases:
29 00000000 ; These are a fabrication that have no direct basis in hardware, but help understanding of the resume process.
30 00000000 ;
31 00000000 ; Resume phase 1 puts the CPU and the platform in a known (default) working state.
32 00000000 ; It is performed by the low level boot code.
33 00000000 ;
34 00000000 ; Phase 2 restores virtual addressing, the CPU core mode, and the stack for that mode.
35 00000000 ; Phase 2 resume data therefore consists of data that is needed on resume to...
36 00000000 ; 1. Restore the MMU.
37 00000000 ; 2. Restore the CPU core to the mode it was in just before power off.
38 00000000 ; 3. Restore the stack pointer for the restored CPU mode.
39 00000000 ;
40 00000000 ; Resume phase 3 (and beyond) restores other CPU and platform state.
41 00000000 ;
42 00000000 ; The routines in this file are used to save state prior to suspend and
43 00000000 ; begin phase 3 of the resume (ie. restore current CPU mode registers).
44 00000000 ; Phase 2 resume is performed in another module linked into the boot loader.
45 00000000 ;
46 00000000 ;**************************************************************************************************
47 00000000 INCLUDE xllp_ARM_macros.inc ; for RETURN macro
1 00000000 IF !:DEF: _xllp_arm_macros_included
2 00000000 xllp_arm_macros_included EQU 1
3 00000000 ;******************************************************************************
4 00000000 ;
5 00000000 ; COPYRIGHT (C) 2005 Intel Corporation.
6 00000000 ;
7 00000000 ; This software as well as the software described in it is furnished under
8 00000000 ; license and may only be used or copied in accordance with the terms of the
9 00000000 ; license. The information in this file is furnished for informational use
10 00000000 ; only, is subject to change without notice, and should not be construed as
11 00000000 ; a commitment by Intel Corporation. Intel Corporation assumes no
12 00000000 ; responsibility or liability for any errors or inaccuracies that may appear
13 00000000 ; in this document or any software that may be provided in association with
14 00000000 ; this document.
15 00000000 ;
16 00000000 ; Except as permitted by such license, no part of this document may be
17 00000000 ; reproduced, stored in a retrieval system, or transmitted in any form or by
18 00000000 ; any means without the express written consent of Intel Corporation.
19 00000000 ;
20 00000000 ;******************************************************************************
21 00000000
22 00000000 MACRO
23 00000000 RETURN
24 00000000 IF :DEF: Interworking
25 00000000 IF Interworking :LOR: Thumbing
26 00000000 bx lr
27 00000000 ELSE
28 00000000 mov pc, lr ; return
29 00000000 ENDIF ; ELSE of IF Interworking :LOR: Thumbing
30 00000000 ELSE ; IF :DEF: Interworking
31 00000000 mov pc, lr ; return
32 00000000 ENDIF ; ELSE OF IF :DEF: Interworking
33 00000000
34 00000000 MEND
35 00000000
36 00000000 ;;------------------------------------------------------------------------------
37 00000000 ENDIF
38 00000000 END
48 00000000 INCLUDE xllp_ResumePhase2_Data.inc ; definition of ResumePhase2 data area
1 00000000 IF !:DEF: _xllp_ResumePhase2_Data_included
2 00000000 xllp_ResumePhase2_Data_included EQU 1
3 00000000 ;******************************************************************************
4 00000000 ;
5 00000000 ; COPYRIGHT (C) 2005 Intel Corporation.
6 00000000 ;
7 00000000 ; This software as well as the software described in it is furnished under
8 00000000 ; license and may only be used or copied in accordance with the terms of the
9 00000000 ; license. The information in this file is furnished for informational use
10 00000000 ; only, is subject to change without notice, and should not be construed as
11 00000000 ; a commitment by Intel Corporation. Intel Corporation assumes no
12 00000000 ; responsibility or liability for any errors or inaccuracies that may appear
13 00000000 ; in this document or any software that may be provided in association with
14 00000000 ; this document.
15 00000000 ;
16 00000000 ; Except as permitted by such license, no part of this document may be
17 00000000 ; reproduced, stored in a retrieval system, or transmitted in any form or by
18 00000000 ; any means without the express written consent of Intel Corporation.
19 00000000 ;
20 00000000 ;******************************************************************************
21 00000000 RESUMEPHASE2_WORD_SIZE EQU 4
22 00000000 RESUMEPHASE2_DATA_START EQU 0
23 00000000
24 00000000 RESUMEPHASE2_CHECKSUM_OFFSET EQU (RESUMEPHASE2_DATA_START)
25 00000000 RESUMEPHASE2_WORDCOUNT_OFFSET EQU (RESUMEPHASE2_CHECKSUM_OFFSET + RESUMEPHASE2_WORD_SIZE)
26 00000000 RESUMEPHASE2_SP_OFFSET EQU (RESUMEPHASE2_WORDCOUNT_OFFSET + RESUMEPHASE2_WORD_SIZE)
27 00000000 RESUMEPHASE2_CPSR_OFFSET EQU (RESUMEPHASE2_SP_OFFSET + RESUMEPHASE2_WORD_SIZE)
28 00000000 RESUMEPHASE2_CPAR_OFFSET EQU (RESUMEPHASE2_CPSR_OFFSET + RESUMEPHASE2_WORD_SIZE)
29 00000000 RESUMEPHASE2_RESUMEPHASE3_PC_OFFSET EQU (RESUMEPHASE2_CPAR_OFFSET + RESUMEPHASE2_WORD_SIZE)
30 00000000 ; Coprocessor registers
31 00000000 RESUMEPHASE2_CP15_ACR_MMU_OFFSET EQU (RESUMEPHASE2_RESUMEPHASE3_PC_OFFSET + RESUMEPHASE2_WORD_SIZE)
32 00000000 RESUMEPHASE2_CP15_AUXCR_MMU_OFFSET EQU (RESUMEPHASE2_CP15_ACR_MMU_OFFSET + RESUMEPHASE2_WORD_SIZE)
33 00000000 RESUMEPHASE2_CP15_TTBR_MMU_OFFSET EQU (RESUMEPHASE2_CP15_AUXCR_MMU_OFFSET + RESUMEPHASE2_WORD_SIZE)
34 00000000 RESUMEPHASE2_CP15_DACR_MMU_OFFSET EQU (RESUMEPHASE2_CP15_TTBR_MMU_OFFSET + RESUMEPHASE2_WORD_SIZE)
35 00000000 RESUMEPHASE2_CP15_PID_MMU_OFFSET EQU (RESUMEPHASE2_CP15_DACR_MMU_OFFSET + RESUMEPHASE2_WORD_SIZE)
36 00000000
37 00000000 RESUMEPHASE2_DATA_END EQU (RESUMEPHASE2_CP15_PID_MMU_OFFSET + RESUMEPHASE2_WORD_SIZE)
38 00000000 RESUMEPHASE2_DATA_SIZE EQU (RESUMEPHASE2_DATA_END - RESUMEPHASE2_DATA_START)
39 00000000 RESUMEPHASE2_DATA_WORDS EQU (RESUMEPHASE2_DATA_SIZE / RESUMEPHASE2_WORD_SIZE)
40 00000000
41 00000000 ENDIF
42 00000000 END
49 00000000 INCLUDE xlli_Bulverde_defs.inc ; Bulverde specific include file
1 00000000 ;*********************************************************************************
2 00000000 ;
3 00000000 ; COPYRIGHT (c) 2002 - 2004 Intel Corporation
4 00000000 ;
5 00000000 ; The information in this file is furnished for informational use only,
6 00000000 ; is subject to change without notice, and should not be construed as
7 00000000 ; a commitment by Intel Corporation. Intel Corporation assumes no
8 00000000 ; responsibility or liability for any errors or inaccuracies that may appear
9 00000000 ; in this document or any software that may be provided in association with
10 00000000 ; this document.
11 00000000 ;
12 00000000 ;*********************************************************************************
13 00000000 ;
14 00000000 ; FILENAME: xlli_Bulverde_defs.inc (Core processor address definitions for PXA27x)
15 00000000 ;
16 00000000 ; LAST MODIFIED: 5-Oct-2004
17 00000000 ;
18 00000000 ;******************************************************************************
19 00000000 ;
20 00000000 ; Include file for PXA27x Processor based
21 00000000 ; Cross Platform Low Level Initialization (XLLI)
22 00000000 ;
23 00000000 ;******************************************************************************
24 00000000
25 00000000
26 00000000 ;
27 00000000 ; Processor stepping Values
28 00000000 ;
29 00000000 xlli_PXA27x_CP15_A0_Val EQU (0x69054110)
30 00000000 xlli_PXA27x_CP15_A1_Val EQU (0x69054111)
31 00000000 xlli_PXA27x_CP15_B0_Val EQU (0x69054112)
32 00000000 xlli_PXA27x_CP15_B1_Val EQU (0x69054113)
33 00000000 xlli_PXA27x_CP15_C0_Val EQU (0x69054114)
34 00000000 xlli_PXA27x_CP15_C5_Val EQU (0x69054117)
35 00000000
36 00000000
37 00000000 xlli_PXA27x_JTAG_A0_Val EQU (0x09265013)
38 00000000 xlli_PXA27x_JTAG_A1_Val EQU (0x19265013)
39 00000000 xlli_PXA27x_JTAG_B0_Val EQU (0x29265013)
40 00000000 xlli_PXA27x_JTAG_B1_Val EQU (0x39265013)
41 00000000 xlli_PXA27x_JTAG_C0_Val EQU (0x49265013)
42 00000000 xlli_PXA27x_JTAG_C5_Val EQU (0x79265013)
43 00000000
44 00000000 xlli_PXA27x_A0_stepping EQU (0x0)
45 00000000 xlli_PXA27x_A1_stepping EQU (0x1)
46 00000000 xlli_PXA27x_B0_stepping EQU (0x2)
47 00000000 xlli_PXA27x_B1_stepping EQU (0x3)
48 00000000 xlli_PXA27x_C0_stepping EQU (0x4)
49 00000000
50 00000000
51 00000000 ;
52 00000000 ; GENERAL PURPOSE I/O (GPIO) base address and register offsets from the base address
53 00000000 ;
54 00000000
55 00000000 xlli_GPIOREGS_PHYSICAL_BASE EQU 0x40E00000
56 00000000
57 00000000 ; GPIO register offsets from the base address
58 00000000
59 00000000 xlli_GPLR0_offset EQU (0x000) ; GPIO Level registers
60 00000000 xlli_GPLR1_offset EQU (0x004)
61 00000000 xlli_GPLR2_offset EQU (0x008)
62 00000000 xlli_GPLR3_offset EQU (0x100)
63 00000000
64 00000000 xlli_GPDR0_offset EQU (0x00C) ; GPIO Direction registers
65 00000000 xlli_GPDR1_offset EQU (0x010)
66 00000000 xlli_GPDR2_offset EQU (0x014)
67 00000000 xlli_GPDR3_offset EQU (0x10C)
68 00000000
69 00000000 xlli_GPSR0_offset EQU (0x018) ; GPIO Set registers
70 00000000 xlli_GPSR1_offset EQU (0x01C)
71 00000000 xlli_GPSR2_offset EQU (0x020)
72 00000000 xlli_GPSR3_offset EQU (0x118)
73 00000000
74 00000000 xlli_GPCR0_offset EQU (0x024) ; GPIO Clear registers
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