📄 xlli_dsplyfreqs.lst
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93 00000000 xlli_GFER3_value EQU (0x0)
94 00000000
95 00000000 xlli_GPLR0_value EQU (0x0) ; Pin Level Registers
96 00000000 xlli_GPLR1_value EQU (0x0)
97 00000000 xlli_GPLR2_value EQU (0x0)
98 00000000 xlli_GPLR3_value EQU (0x0)
99 00000000
100 00000000 xlli_GEDR0_value EQU (0x0) ; Edge Detect Status
101 00000000 xlli_GEDR1_value EQU (0x0)
102 00000000 xlli_GEDR2_value EQU (0x0)
103 00000000 xlli_GEDR3_value EQU (0x0)
104 00000000
105 00000000 IF :DEF: POST_BUILD
112 00000000 ELSE
113 00000000
114 00000000 xlli_GPDR0_value EQU (0xCFE3BDE4) ; Direction Registers
115 00000000 xlli_GPDR1_value EQU (0x003FAB81)
116 00000000 xlli_GPDR2_value EQU (0x1EC3FC00)
117 00000000 xlli_GPDR3_value EQU (0x018FFE8F)
118 00000000
119 00000000 ENDIF
120 00000000
121 00000000 xlli_GAFR0_L_value EQU (0x84400000) ; Alternate function registers
122 00000000 xlli_GAFR0_U_value EQU (0xA5000510)
123 00000000 xlli_GAFR1_L_value EQU (0x000A9558)
124 00000000 xlli_GAFR1_U_value EQU (0x0005A1AA)
125 00000000 xlli_GAFR2_L_value EQU (0x60000000)
126 00000000 xlli_GAFR2_U_value EQU (0x00000802)
127 00000000 xlli_GAFR3_L_value EQU (0x00000000)
128 00000000 xlli_GAFR3_U_value EQU (0x00000000)
129 00000000
130 00000000 ;
131 00000000 ; MEMORY CONTROLLER SETTINGS FOR MAINSTONE
132 00000000 ;
133 00000000
134 00000000 xlli_MDREFR_value EQU (0x0000001E)
135 00000000 IF :DEF: xlli_FLASH_WIDTH_16_BIT
137 00000000 ELSE
138 00000000 xlli_MSC0_DC_value EQU (0x7FF0B8F2) ; PXA27x Card Flash value (Non-MCP version)
139 00000000 ENDIF
140 00000000 xlli_MSC0_MS_value EQU (0x23F2B8F2) ; Mainstone Board Flash value
141 00000000 xlli_MSC1_value EQU (0x0000CCD1)
142 00000000 xlli_MSC2_value EQU (0x0000B884)
143 00000000 xlli_MECR_value EQU (0x00000001)
144 00000000 xlli_MCMEM0_value EQU (0x00014307)
145 00000000 xlli_MCMEM1_value EQU (0x00014307)
146 00000000 xlli_MCATT0_value EQU (0x0001C787)
147 00000000 xlli_MCATT1_value EQU (0x0001C787)
148 00000000 xlli_MCIO0_value EQU (0x0001430F)
149 00000000 xlli_MCIO1_value EQU (0x0001430F)
150 00000000 xlli_FLYCNFG_value EQU (0x00010001)
151 00000000 xlli_MDMRSLP_value EQU (0x0000C008)
152 00000000 xlli_SXCNFG_value EQU (0x40044004) ; Default value at boot up
153 00000000
154 00000000
155 00000000 ;
156 00000000 ; Optimal values for MSCO for various MemClk frequencies are listed below
157 00000000 ; These values are for L18 async flash
158 00000000 ;
159 00000000 IF :DEF: xlli_C0_BULVERDE
160 00000000
161 00000000 xlli_MSC0_13 EQU (0x11101110)
162 00000000 xlli_MSC0_19 EQU (0x11101110)
163 00000000 xlli_MSC0_26 EQU (0x11201120) ; 26 MHz setting
164 00000000 xlli_MSC0_32 EQU (0x11201120)
165 00000000 xlli_MSC0_39 EQU (0x11301130) ; 39 MHz setting
166 00000000 xlli_MSC0_45 EQU (0x11301130)
167 00000000 xlli_MSC0_52 EQU (0x11401140) ; 52 MHz setting
168 00000000 xlli_MSC0_58 EQU (0x11401140)
169 00000000 xlli_MSC0_65 EQU (0x11501150) ; 65 MHz setting
170 00000000 xlli_MSC0_68 EQU (0x11501150)
171 00000000 xlli_MSC0_71 EQU (0x11501150) ; 71.5 MHz setting
172 00000000 xlli_MSC0_74 EQU (0x11601160)
173 00000000 xlli_MSC0_78 EQU (0x12601260) ; 78 MHz setting
174 00000000 xlli_MSC0_81 EQU (0x12601260)
175 00000000 xlli_MSC0_84 EQU (0x12601260) ; 84.5 MHz setting
176 00000000 xlli_MSC0_87 EQU (0x12701270)
177 00000000 xlli_MSC0_91 EQU (0x12701270) ; 91 MHz setting
178 00000000 xlli_MSC0_94 EQU (0x12701270) ; 94.2 MHz setting
179 00000000 xlli_MSC0_97 EQU (0x12701270) ; 97.5 MHz setting
180 00000000 xlli_MSC0_100 EQU (0x12801280) ; 100.7 MHz setting
181 00000000 xlli_MSC0_104 EQU (0x12801280) ; 104 MHz setting
182 00000000 xlli_MSC0_110 EQU (0x12901290)
183 00000000 xlli_MSC0_117 EQU (0x13901390) ; 117 MHz setting
184 00000000 xlli_MSC0_124 EQU (0x13A013A0)
185 00000000 xlli_MSC0_130 EQU (0x13A013A0) ; 130 MHz setting
186 00000000 xlli_MSC0_136 EQU (0x13B013B0)
187 00000000 xlli_MSC0_143 EQU (0x13B013B0)
188 00000000 xlli_MSC0_149 EQU (0x13C013C0)
189 00000000 xlli_MSC0_156 EQU (0x14C014C0)
190 00000000 xlli_MSC0_162 EQU (0x14C014C0)
191 00000000 xlli_MSC0_169 EQU (0x14C014C0)
192 00000000 xlli_MSC0_175 EQU (0x14C014C0)
193 00000000 xlli_MSC0_182 EQU (0x14C014C0)
194 00000000 xlli_MSC0_188 EQU (0x14C014C0)
195 00000000 xlli_MSC0_195 EQU (0x15C015C0)
196 00000000 xlli_MSC0_201 EQU (0x15D015D0)
197 00000000 xlli_MSC0_208 EQU (0x15D015D0)
198 00000000
199 00000000 ELSE
241 00000000 ENDIF ; xlli_C0_BULVERDE
242 00000000
243 00000000 ;
244 00000000 ; Optimal values for DTC settings for various MemClk settings (MDCNFG)
245 00000000 ;
246 00000000 IF :DEF: xlli_SDRAM_WIDTH_16_BIT
331 00000000 ELSE ; ELSE not 16 bit SDRAM width
332 00000000
333 00000000 xlli_DTC_13 EQU (0x00000000) ; 13 MHz setting
334 00000000 xlli_DTC_19 EQU (0x00000000) ; 19 MHz setting
335 00000000 xlli_DTC_26 EQU (0x00000000) ; 26 MHz setting
336 00000000 xlli_DTC_32 EQU (0x00000000) ; 32 MHz setting
337 00000000 xlli_DTC_39 EQU (0x00000000) ; 39 MHz setting
338 00000000 xlli_DTC_45 EQU (0x00000000) ; 45 MHz setting
339 00000000 xlli_DTC_52 EQU (0x00000000) ; 52 MHz setting
340 00000000 xlli_DTC_58 EQU (0x01000100) ; 58 MHz setting
341 00000000 xlli_DTC_65 EQU (0x01000100) ; 65 MHz setting
342 00000000 xlli_DTC_68 EQU (0x01000100) ; 68 MHz setting
343 00000000 xlli_DTC_71 EQU (0x01000100) ; 71 MHz setting
344 00000000 xlli_DTC_74 EQU (0x01000100) ; 74 MHz setting
345 00000000 xlli_DTC_78 EQU (0x01000100) ; 78 MHz setting
346 00000000 xlli_DTC_81 EQU (0x01000100) ; 81 MHz setting
347 00000000 xlli_DTC_84 EQU (0x01000100) ; 84 MHz setting
348 00000000 xlli_DTC_87 EQU (0x01000100) ; 87 MHz setting
349 00000000 xlli_DTC_91 EQU (0x02000200) ; 91 MHz setting
350 00000000 xlli_DTC_94 EQU (0x02000200) ; 94 MHz setting
351 00000000 xlli_DTC_97 EQU (0x02000200) ; 97 MHz setting
352 00000000 xlli_DTC_100 EQU (0x02000200) ; 100 MHz setting
353 00000000 xlli_DTC_104 EQU (0x02000200) ; 104 MHz setting
354 00000000 xlli_DTC_110 EQU (0x01000100) ; 110 MHz setting - SDCLK Halved
355 00000000 xlli_DTC_117 EQU (0x01000100) ; 117 MHz setting - SDCLK Halved
356 00000000 xlli_DTC_124 EQU (0x01000100) ; 124 MHz setting - SDCLK Halved
357 00000000 xlli_DTC_130 EQU (0x01000100) ; 130 MHz setting - SDCLK Halved
358 00000000 xlli_DTC_136 EQU (0x01000100) ; 136 MHz setting - SDCLK Halved
359 00000000 xlli_DTC_143 EQU (0x01000100) ; 143 MHz setting - SDCLK Halved
360 00000000 xlli_DTC_149 EQU (0x01000100) ; 149 MHz setting - SDCLK Halved
361 00000000 xlli_DTC_156 EQU (0x01000100) ; 156 MHz setting - SDCLK Halved
362 00000000 xlli_DTC_162 EQU (0x01000100) ; 162 MHz setting - SDCLK Halved
363 00000000 xlli_DTC_169 EQU (0x01000100) ; 169 MHz setting - SDCLK Halved
364 00000000 xlli_DTC_175 EQU (0x01000100) ; 175 MHz setting - SDCLK Halved
365 00000000 xlli_DTC_182 EQU (0x02000200) ; 182 MHz setting - SDCLK Halved - Close to edge, so bump up
366 00000000 xlli_DTC_188 EQU (0x02000200) ; 188 MHz setting - SDCLK Halved - Close to edge, so bump up
367 00000000 xlli_DTC_195 EQU (0x02000200) ; 195 MHz setting - SDCLK Halved - Close to edge, so bump up
368 00000000 xlli_DTC_201 EQU (0x02000200) ; 201 MHz setting - SDCLK Halved - Close to edge, so bump up
369 00000000 xlli_DTC_208 EQU (0x02000200) ; 208 MHz setting - SDCLK Halved - Close to edge, so bump up
370 00000000
371 00000000 ;
372 00000000 ; Optimal values for DRI settings for various MemClk settings (MDREFR)
373 00000000 ;
374 00000000 xlli_DRI_13 EQU (0x002) ; 13 MHz setting
375 00000000 xlli_DRI_19 EQU (0x003)
376 00000000 xlli_DRI_26 EQU (0x005) ; 26 MHz setting
377 00000000 xlli_DRI_32 EQU (0x006)
378 00000000 xlli_DRI_39 EQU (0x008) ; 39 MHz setting
379 00000000 xlli_DRI_45 EQU (0x00A)
380 00000000 xlli_DRI_52 EQU (0x00B) ; 52 MHz setting
381 00000000 xlli_DRI_58 EQU (0x00D)
382 00000000 xlli_DRI_65 EQU (0x00E) ; 65 MHz setting
383 00000000 xlli_DRI_68 EQU (0x00F)
384 00000000 xlli_DRI_71 EQU (0x010) ; 71 MHz setting
385 00000000 xlli_DRI_74 EQU (0x011)
386 00000000 xlli_DRI_78 EQU (0x012) ; 78 MHz setting
387 00000000 xlli_DRI_81 EQU (0x012)
388 00000000 xlli_DRI_84 EQU (0x013) ; 84 MHz setting
389 00000000 xlli_DRI_87 EQU (0x014)
390 00000000 xlli_DRI_91 EQU (0x015) ; 91 MHz setting
391 00000000 xlli_DRI_94 EQU (0x016) ; 94 MHz setting
392 00000000 xlli_DRI_97 EQU (0x016) ; 97 MHz setting
393 00000000 xlli_DRI_100 EQU (0x017) ; 100 MHz setting
394 00000000 xlli_DRI_104 EQU (0x018) ; 104 MHz setting
395 00000000 xlli_DRI_110 EQU (0x01A)
396 00000000 xlli_DRI_117 EQU (0x01B) ; 117 MHz setting
397 00000000 xlli_DRI_124 EQU (0x01D)
398 00000000 xlli_DRI_130 EQU (0x01E) ; 130 MHz setting
399 00000000 xlli_DRI_136 EQU (0x020)
400 00000000 xlli_DRI_143 EQU (0x021)
401 00000000 xlli_DRI_149 EQU (0x023)
402 00000000 xlli_DRI_156 EQU (0x025)
403 00000000 xlli_DRI_162 EQU (0x026)
404 00000000 xlli_DRI_169 EQU (0x028) ; 169 MHz setting
405 00000000 xlli_DRI_175 EQU (0x029)
406 00000000 xlli_DRI_182 EQU (0x02B)
407 00000000 xlli_DRI_188 EQU (0x02D)
408 00000000 xlli_DRI_195 EQU (0x02E)
409 00000000 xlli_DRI_201 EQU (0x030)
410 00000000 xlli_DRI_208 EQU (0x031) ; 208 MHz setting
411 00000000
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