dl_uart.c
来自「在高通的手机平台下,一个下载手机.bin文件到手机的flash中的工具,包含PC」· C语言 代码 · 共 491 行 · 第 1/2 页
C
491 行
/*===========================================================================
INCLUDE FILES FOR MODULE
===========================================================================*/
/*
when who what, where, why
-------- -------- ---------------------------------------------------------------
01/27/05 nony.wu Added change baud rate command
============================================================================ */
#include "dl_uart.h"
#include "dl_proc.h"
#define FLASH0_CFG_WW 0x0a0000d0
#define SRAM0_CFG_WW 0x0a0000d8
#define MSM_CLK_HALT_WW 0x03000600
#define MSM_CLK_SRCSEL1_WW 0x03000614
#define MSM_CLK_HALT_WW__UART1_CLK_HALT_MASK 0x2
#define MSM_CLK_SRCSEL1_WW__UART1_CLK_SRC_SEL_MASK 0xc000
#define MSM_CLK_CTL1_WH 0x03000740
#define MSM_CLK_CTL1_WH_MASK 0xffff
#define MSM_CLK_CTL1_WH__CDMA_PDM_EN_N_MASK 0x8000
#define MSM_CLK_CTL1_WH__CDMA_AGC_EN_N_MASK 0x4000
#define MSM_CLK_CTL1_WH__RXFRONT_EN_N_MASK 0x2000
#define MSM_CLK_CTL1_WH__CODEC_CORE_EN_N_MASK 0x1000
#define MSM_CLK_CTL1_WH__DEC_CLK_EN_N_MASK 0x800
#define MSM_CLK_CTL1_WH__RXCX8_BYPASS_MASK 0x400
#define MSM_CLK_CTL1_WH__CDMA_RXDSP_CLK_EN_N_MASK 0x200
#define MSM_CLK_CTL1_WH__SBI_CLK_EN_N_MASK 0x100
#define MSM_CLK_CTL1_WH__MICRO_INTF_BYPASS_MASK 0x80
#define MSM_CLK_CTL1_WH__VOC_CLK_EN_N_MASK 0x40
#define MSM_CLK_CTL1_WH__CODECIF_CLK_EN_N_MASK 0x20
#define MSM_CLK_CTL1_WH__DFM_CLK_EN_N_MASK 0x10
#define MSM_CLK_CTL1_WH__CDMA_RX_CLK_EN_N_MASK 0x8
#define MSM_CLK_CTL1_WH__CDMA_TX_CLK_EN_N_MASK 0x4
#define MSM_CLK_CTL1_WH__UART_CLK_EN_N_MASK 0x2
#define MSM_CLK_CTL1_WH__GENERAL_CLK_EN_N_MASK 0x1
#define MSM_CLK_CTL2_WH 0x03000744
#define MSM_CLK_CTL2_WH_MASK 0xffff
#define MSM_CLK_CTL2_WH__CDMA_PDM_CLK_MASK 0x8000
#define MSM_CLK_CTL2_WH__CDMA_AGC_CLK_MASK 0x4000
#define MSM_CLK_CTL2_WH__RXFRONT_CLK_MASK 0x2000
#define MSM_CLK_CTL2_WH__CODEC_CORE_CLK_MASK 0x1000
#define MSM_CLK_CTL2_WH__DEC_CLK_MASK 0x800
#define MSM_CLK_CTL2_WH__UNUSED_MASK 0x400
#define MSM_CLK_CTL2_WH__CDMA_RXDSP_CLK_MASK 0x200
#define MSM_CLK_CTL2_WH__SBI_CLK_MASK 0x100
#define MSM_CLK_CTL2_WH__RESERVED_7_MASK 0x80
#define MSM_CLK_CTL2_WH__VOC_CLK_MASK 0x40
#define MSM_CLK_CTL2_WH__CODECIF_CLK_MASK 0x20
#define MSM_CLK_CTL2_WH__DFM_CLK_MASK 0x10
#define MSM_CLK_CTL2_WH__CDMA_RX_CLK_MASK 0x8
#define MSM_CLK_CTL2_WH__CDMA_TX_CLK_MASK 0x4
#define MSM_CLK_CTL2_WH__UART_CLK_MASK 0x2
#define MSM_CLK_CTL2_WH__GENERAL_CLK_MASK 0x1
#define CLK_RGM_ENABLE 0x0000
#define CLK_RGM_DISABLE 0xFFFF
#define CLK_RGM_CLEAR 0x0000
#define CLK_RGM_SET 0xFFFF
#define CLK_RGM_MISC_ENA 0xFF
#define CLK_RGM_MISC_DIS 0x00
#define SHIFT_TEST( val , shift ) ( (val) & (1U << (shift)) )
#define SHIFT_GET( val, shift, next_shift) (SHIFT_TEST((val),(shift)) ? \
(shift) : (next_shift))
#define SHIFT_FROM_MASK(x) (SHIFT_TEST(x##_MASK,0) ? 0 : \
(SHIFT_GET(x##_MASK,1, \
(SHIFT_GET(x##_MASK,2, \
(SHIFT_GET(x##_MASK,3, \
(SHIFT_GET(x##_MASK,4, \
(SHIFT_GET(x##_MASK,5, \
(SHIFT_GET(x##_MASK,6, \
(SHIFT_GET(x##_MASK,7, \
(SHIFT_GET(x##_MASK,8, \
(SHIFT_GET(x##_MASK,9, \
(SHIFT_GET(x##_MASK,10, \
(SHIFT_GET(x##_MASK,11, \
(SHIFT_GET(x##_MASK,12, \
(SHIFT_GET(x##_MASK,13, \
(SHIFT_GET(x##_MASK,14, \
(SHIFT_GET(x##_MASK,15, \
(SHIFT_GET(x##_MASK,16, \
(SHIFT_GET(x##_MASK,17, \
(SHIFT_GET(x##_MASK,18, \
(SHIFT_GET(x##_MASK,19, \
(SHIFT_GET(x##_MASK,20, \
(SHIFT_GET(x##_MASK,21, \
(SHIFT_GET(x##_MASK,22, \
(SHIFT_GET(x##_MASK,23, \
(SHIFT_GET(x##_MASK,24, \
(SHIFT_GET(x##_MASK,25, \
(SHIFT_GET(x##_MASK,26, \
(SHIFT_GET(x##_MASK,27, \
(SHIFT_GET(x##_MASK,28, \
(SHIFT_GET(x##_MASK,29, \
(SHIFT_GET(x##_MASK,30, \
(SHIFT_GET(x##_MASK,31,0) \
) )))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))
#define MSM_CLK_SRCSEL1_WW__UART1_CLK_SRC_SEL_TCXODIV4 (0U << \
SHIFT_FROM_MASK(MSM_CLK_SRCSEL1_WW__UART1_CLK_SRC_SEL))
#define MSM_CLK_SRCSEL1_WW__UART1_CLK_SRC_SEL_TCXO (2U << \
SHIFT_FROM_MASK(MSM_CLK_SRCSEL1_WW__UART1_CLK_SRC_SEL))
#define CLK_RGM_UART_SRC_TCXODIV4_V MSM_CLK_SRCSEL1_WW__UART1_CLK_SRC_SEL_TCXODIV4
#define CLK_RGM_UART_SRC_TCXO MSM_CLK_SRCSEL1_WW__UART1_CLK_SRC_SEL_TCXO
/*===========================================================================
FUNCTION MCLK_REINITIAL
DESCRIPTION
This function reinitials the system waiting state for flash and ram.
RETURN VALUE
None.
SIDE EFFECTS
None.
===========================================================================*/
void mclk_reinit(void)
{
int i;
/*
#define FLASH0_CFG_PAGE_SIZE_TCXO_P 0x0 8 word page
#define FLASH0_CFG_CS_SETUP_TCXO_P 0x0 For PSRAM (not necessary)
#define FLASH0_CFG_RECOVERY_TCXO_P 0x0 CS turnover, read then write
#define FLASH0_CFG_HOLD_WAIT_TCXO_P 0x1 Dead Wait states
#define FLASH0_CFG_DELTA_WR_TCXO_P 0x0 Extra wait states to add for first word in page
#define FLASH0_CFG_DELTA_RD_TCXO_P 0x0 Extra wait states to add for first word in page
#define FLASH0_CFG_WAIT_WR_TCXO_P 0x6 Min. wait states to write word in page (min 1)
#define FLASH0_CFG_WAIT_RD_TCXO_P 0x6 Min. wait states to read word in page
*/
outpdw(FLASH0_CFG_WW, 0x00010055);
/* make sure the system can work well, so add a 100*100-ns delay. */
for(i=0; i<100; i++) {
__asm {
NOP
NOP
NOP
}
}
}
/*===========================================================================
FUNCTION uart_drain
DESCRIPTION
This function waits for the last character in the UART's transmit
FIFO to be transmitted. This allows the caller to be sure that all
characters are transmitted.
DEPENDENCIES
If the transmit FIFO is not empty, the UART must be initialized enough
for it to eventually empty itself, or else this routine will wait
forever.
RETURN VALUE
None.
SIDE EFFECTS
The watchdog is reset.
===========================================================================*/
void uart_drain(void)
{
/*- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
/* Wait while the UART's transmitter drains. This lets the ACK to
the GO command that started FLASHPRG get back to the PC before
we reset the UART. */
while ( ( inp(UART_SR) & UART_SR_TXEMT ) == 0)
{
BOOTHW_KICK_WATCHDOG(); /* Don't let the watchdog expire while we wait */
}
}/* uart_drain() */
/*===========================================================================
FUNCTION dload_uart_init
DESCRIPTION
This function initializes the MSM 3000 UART to 115,200 bps, 8N1, with
no interrupts enabled but both receiver and transmitter running.
Before initializing the UART, this function waits for the UART's
transmit buffer to empty out. This permits the ACK to the GO
command that started the program (or any other pending transmission)
to get back to the host, instead of being lost when the UART is
reset.
DEPENDENCIES
If the transmit FIFO is not empty, the UART must be initialized enough
for it to eventually empty itself, or else this routine will wait
forever.
RETURN VALUE
None.
SIDE EFFECTS
The watchdog is reset.
===========================================================================*/
void dload_uart_init(word baud_rate)
{
int chr; /* character variable for RX FIFO drain */
/*- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
/* Code copied from clk_rgm_sel(). We do not want to depend on code outside
the boot code memory area. */
MSMUW_OUT(UART_CLK_SEL_REG,UART_CLK_SEL_TCXO);
/* drain anything in the UART */
uart_drain();
(void) MSMU_OUT(UART_MVR, UART_MVR_V); /* M register LSB */
(void) MSMU_OUT(UART_NVR, UART_NVR_V); /* N register LSB */
(void) MSMU_OUT(UART_DVR, UART_DVR_V); /* D register LSB */
(void) MSMU_OUT(UART_MNDR, UART_MNDR_V); /* MSBs of M, N, and D */
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