dl_uart.h
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H
364 行
#ifndef __DL_UART_H__
#define __DL_UART_H__
/*===========================================================================
INCLUDE FILES FOR MODULE
===========================================================================*/
/*
when who what, where, why
-------- -------- ---------------------------------------------------------------
01/27/05 nony.wu Added change baud rate command
============================================================================ */
#include "dl_comm.h"
/*===========================================================================
LOCAL DEFINITIONS AND DECLARATIONS FOR MODULE
This section contains local definitions for constants, macros, types,
variables and other items needed by this module.
===========================================================================*/
/* Error return code from uart_receive_byte */
/* This int value must not be any valid unsigned char value. */
#define UART_RX_ERR (-1)
#define UART_TIMEOUT (-2)
#define UART_NO_CHAR (-3)
/* Following definitions are added by Fraser.wang, the value may be wrong */
#define UART_SR_BREAK_RXD 0x40 /* break received */
#define UART_SR_PF_ERR 0x20 /* Parity or Framing error */
#define UART_ISR_TXLEV 0x01 /* tx FIFO at or below the mark */
#define UART_MR2_8BPC 0x30 /* 8 bits per character */
#define UART_MR2_1SB 0x04 /* 1 stop bit */ // ??? Maybe oxoc
#define UART_CR_RESET_ERR 0x30 /* reset error status */ //??? Maybe oxf0
#define UART_CR_RESET_RX 0x10 /* reset receiver */ // ??? Maybe oxf0
#define UART_CR_RX_ENA 0x01 /* enable receiver */ //
#define UART_CR_RESET_TX 0x20 /* reset transmitter */ // ??? Maybe oxf0
#define UART_CR_TX_ENA 0x04 /* enable transmitter */ //
#define UART_SR_RXRDY 0x01 /* Receiver ready */
#define UART_SR_TXEMT 0x08 /* Transmitter empty */
/* Following definition of UART register are added by Fraser.wang */
//-----------------------------------------------------------------------------
// SECTION UART WRITE REGISTERS (0xB00 to 0xB7C)
//-----------------------------------------------------------------------------
#define UART_MR1_WB 0x030007ac
#define UART_MR1_WB_MASK 0x7ff
#define UART_MR1_WB__AUTO_RFR_LEVEL_MASK 0x3f
#define UART_MR1_WB__RX_RDY_CTL_MASK 0x80
#define UART_MR1_WB__CTS_CTL_MASK 0x40
#define UART_MR1_WB__AUTO_RFR_LEVEL_MASK 0x3f
#define UART_MR2_WB 0x030007b0
#define UART_MR2_WB_MASK 0xff
#define UART_MR2_WB__LOOPBACK_MASK 0x80
#define UART_MR2_WB__ERROR_MODE_MASK 0x40
#define UART_MR2_WB__BITS_PER_CHAR_MASK 0x30
#define UART_MR2_WB__STOP_BIT_LEN_MASK 0xc
#define UART_MR2_WB__PARITY_MODE_MASK 0x3
#define UART_CSR_WB 0x030007b4
#define UART_CSR_WB_MASK 0xff
#define UART_CSR_WB__UART_RX_CLK_SEL_MASK 0xf0
#define UART_CSR_WB__UART_TX_CLK_SEL_MASK 0xf
#define UART_TF_WB 0x030007b8
#define UART_TF_WB_MASK 0xff
#define UART_CR_WB 0x030007bc
#define UART_CR_WB_MASK 0xff
#define UART_CR_WB__CHANNEL_COMMAND_MASK 0xf0
#define UART_CR_WB__UART_TX_DISBALE_MASK 0x8
#define UART_CR_WB__UART_TX_EN_MASK 0x4
#define UART_CR_WB__UART_RX_DISABLE_MASK 0x2
#define UART_CR_WB__UART_RX_EN_MASK 0x1
#define UART_IMR_WB 0x030007c0
#define UART_IMR_WB_MASK 0x7f
#define UART_IMR_WB__CURRENT_CTS_MASK 0x40
#define UART_IMR_WB__DELTA_CTS_MASK 0x20
#define UART_IMR_WB__RXLEV_MASK 0x10
#define UART_IMR_WB__RXSTALE_MASK 0x8
#define UART_IMR_WB__RXBREAK_MASK 0x4
#define UART_IMR_WB__RXHUNT_MASK 0x2
#define UART_IMR_WB__TXLEV_MASK 0x1
#define UART_TFWR_WB 0x030007c8
#define UART_TFWR_WB_MASK 0x1ff
#define UART_TFWR_WB__TFW_MASK 0x1ff
#define UART_RFWR_WB 0x030007cc
#define UART_RFWR_WB_MASK 0x1ff
#define UART_RFWR_WB__RFW_MASK 0x1ff
#define UART_HCR_WB 0x03000b30
#define UART_HCR_WB_MASK 0xff
#define UART_MREG_WB 0x030007d4
#define UART_MREG_WB_MASK 0xff
#define UART_NREG_WB 0x030007d8
#define UART_NREG_WB_MASK 0xff
#define UART_DREG_WB 0x030007dc
#define UART_DREG_WB_MASK 0xff
#define UART_MNDREG_WB 0x030007e0
#define UART_MNDREG_WB_MASK 0x3f
#define UART_MNDREG_WB__MREG_LSB_MASK 0x20
#define UART_MNDREG_WB__NREG_LSB_MASK 0x1c
#define UART_MNDREG_WB__DREG_LSB_MASK 0x3
//-----------------------------------------------------------------------------
// SECTION UART READ REGISTERS (0xB00 to 0xB7C)
//-----------------------------------------------------------------------------
#define UART_SR_RB 0x030007b4
#define UART_SR_RB_MASK 0xff
#define UART_SR_RB__HUNT_CHAR_MASK 0x80
#define UART_SR_RB__RX_BREAK_MASK 0x40
#define UART_SR_RB__PAR_FRAME_ERR_MASK 0x20
#define UART_SR_RB__UART_OVERRUN_MASK 0x10
#define UART_SR_RB__TXEMT_MASK 0x8
#define UART_SR_RB__TXRDY_MASK 0x4
#define UART_SR_RB__RXFULL_MASK 0x2
#define UART_SR_RB__RXRDY_MASK 0x1
#define UART_RF_RB 0x030007b8
#define UART_RF_RB_MASK 0xff
#define UART_ISR_RB 0x030007c0
#define UART_ISR_RB_MASK 0x7f
#define UART_ISR_RB__CURRENT_CTS_MASK 0x40
#define UART_ISR_RB__DELTA_CTS_MASK 0x20
#define UART_ISR_RB__RXLEV_MASK 0x10
#define UART_ISR_RB__RXSTALE_MASK 0x8
#define UART_ISR_RB__RXBREAK_MASK 0x4
#define UART_ISR_RB__RXHUNT_MASK 0x2
#define UART_ISR_RB__TXLEV_MASK 0x1
#define MSM_CLK_CTL7_WH 0x03000730
#define MSM_CLK_CTL7_WH_MASK 0xffff
#define MSM_CLK_CTL7_WH__CDMA_CHIP_TEST_CLK_SEL_MASK 0xc000
#define MSM_CLK_CTL7_WH__UART_CLK_SEL_MASK 0x3000
#define MSM_CLK_CTL7_WH__RESERVED_11_MASK 0x800
#define MSM_CLK_CTL7_WH__RXDSP_CLK_SEL_MASK 0x600
#define MSM_CLK_CTL7_WH__RESERVED_8_MASK 0x100
#define MSM_CLK_CTL7_WH__CODEC_CLK_SEL_MASK 0xf0
#define MSM_CLK_CTL7_WH__SBI_CLK_SEL_MASK 0xc
#define MSM_CLK_CTL7_WH__DEC_CLK_SEL_MASK 0x3
/* Following definitions are added by Fraser.wang */
#define UART_MVR UART_MREG_WB
#define UART_NVR UART_NREG_WB
#define UART_DVR UART_DREG_WB
#define UART_MNDR UART_MNDREG_WB
#define UART_MR1 UART_MR1_WB
#define UART_TXWAT UART_TFWR_WB
#define UART_RXWAT UART_RFWR_WB
#define UART_MR2 UART_MR2_WB
#define UART_SR UART_SR_RB
#define UART_CSR UART_CSR_WB
#define UART_RFIFO UART_RF_RB
#define UART_TFIFO UART_TF_WB
#define UART_CR UART_CR_WB
#define UART_ISR UART_ISR_RB
#define UART_IMR UART_IMR_WB
#define TIMEOUT_ENABLED TRUE
#define TIMEOUT_DISABLED FALSE
/* Following definitions are added by Fraser.wang */
/* ----------------------------------------------------------------------- */
/* Calculate the proper M, N, D, and MND register values */
/* ----------------------------------------------------------------------- */
#define M_VAL (unsigned)384 /* M value (9 bits) */
#define N_VAL (unsigned)1000 /* N value (11 bits) */
#define D_VAL (unsigned)500 /* D value - half of N_VAL (10 bits) */
#define N_MINUS_M_VAL (unsigned)((0x7ff - (N_VAL - M_VAL))) /* '(N-M) */
#define M_REG_VAL (byte) ( (M_VAL & 0x1fe)>>1 ) /* MS 8/9 bits */
#define N_REG_VAL (byte) ( (N_MINUS_M_VAL & 0x7f8) >> 3 ) /* MS 8/11 bits */
#define D_REG_VAL (byte) ( (D_VAL & 0x3fc) >> 2 ) /* MS 8/10 bits */
#define MND_REG_VAL (byte) ( ((M_VAL & 0x01) << 5) | \
((N_MINUS_M_VAL & 0x07 ) << 2) | \
(D_VAL & 0x3) )
/* LS 1 bit of M, LS 3 bits of N, and LS 2 bits of D */
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