boothw_6000.c

在高通的手机平台下,一个下载手机.bin文件到手机的flash中的工具,包含PC端的程序代码和运行在基带处理器中的代码.

    None.

  SIDE EFFECTS
    The MSM chip is initialized.
===========================================================================*/
void
boot_hw_tlmm_init()
{
/***********************************************************************************************
 *** Warning: This routine can make no function calls and reference no global data since we  ***
 ***          are still in rom and have no stacks yet.                                       ***
 ***********************************************************************************************/

  register word counter = 0;

/*  This array contains the addr and initial value for each register
    that needs to be initialized to enable several gpios to a specific
    mode*/
  //while(GpioFuncSelInit[counter].addr != NULL)
  {
    //outpw(GpioFuncSelInit[counter].addr, GpioFuncSelInit[counter].val);
    //counter++;
   outpw(GpioFuncSelInit[0].addr, 0x0010);
   outpw(GpioFuncSelInit[1].addr, 0x2000);
   outpw(GpioFuncSelInit[2].addr, 0x0100);
  }

  /* Configure UP_CLK_CTL1 */
  //outp( UP_CLK_CTL1_WB,  UP_CLK_CTL1_WB__POWER_DOWN_DIS |
   //                      UP_CLK_CTL1_WB__XTAL_WU_DURATION_52USEC |
   //                      UP_CLK_CTL1_WB__UP_CLK_SRC_TCXO );

  outp( UP_CLK_CTL1_WB,  0x4);

  /* Configure UP_CLK_CTL2 */
  /* MSM3100 Watch-dog timeout or RESIN_N default is divide by 1 */
  //outp( UP_CLK_CTL2_WB,  UP_CLK_CTL2_WB__MCLK_RATE_DIV1 );
  outp( UP_CLK_CTL2_WB,  0x0);

  /* Configure TCXO and SLEEP Xtal clocks via MSM_CLK_CTL4.
  ** This register can be written only once on power-up!
  */
//#ifdef FEATURE_SLEEP_SLOW_CLOCK
  /* Configure MSM_CLK_CTL4 */
  /* Select the low frequency range [30 KHz - 60 KHz] */
//#if defined(FEATURE_PMIC_32K_XTAL)
  /* Use the sleep clock from PMIC */
  //outpw( MSM_CLK_CTL4_WH, MSM_CLK_CTL4_WH__SLEEP_XTAL_EN_ENA       |
  //                        MSM_CLK_CTL4_WH__SLEEP_OSC_RF_BYPASS_ENA |
  //                        MSM_CLK_CTL4_WH__SLEEP_OSC_RD_BYPASS_DIS |
  //                        MSM_CLK_CTL4_WH__SLEEP_OSC_GAIN_001      |
  //                        BOOT_HW_TCXO_SEL );
 outpw( MSM_CLK_CTL4_WH, 0x4680);
  
//#else
 // outpw( MSM_CLK_CTL4_WH, MSM_CLK_CTL4_WH__SLEEP_XTAL_EN_ENA       |
//                          MSM_CLK_CTL4_WH__SLEEP_OSC_RD_BYPASS_ENA |
//                          MSM_CLK_CTL4_WH__SLEEP_OSC_GAIN_000      |
//                          BOOT_HW_TCXO_SEL );
//#endif /* FEATURE_PMIC_32K_XTAL*/
//#else
  /* Configure MSM_CLK_CTL4 */
//  outpw( MSM_CLK_CTL4_WH, MSM_CLK_CTL4_WH__SLEEP_XTAL_EN_DIS       |
 //                         MSM_CLK_CTL4_WH__SLEEP_OSC_RD_BYPASS_DIS |
//                          MSM_CLK_CTL4_WH__SLEEP_OSC_GAIN_000      |
//                          BOOT_HW_TCXO_SEL );
//#endif /* FEATURE_SLEEP_SLOW_CLOCK */
  
/*--------------------------------------------------------------------------*/
/* Initialize MSM Reserved Registers                                        */
/*--------------------------------------------------------------------------*/
  
/* For correct operation clear these registers */
  outpw( MSM_CLK_CTL2_WH, 0x0000 );   /* MSM_CLK_CTL1_WH ... 0x03000740 */
  outpw( MSM_CLK_CTL1_WH, 0x0000 );   /* MSM_CLK_CTL1_WH ... 0x03000740 */


  outp ( VD_TESTCON_WB, 0x00 );        /* VD_TESTCON ... 0x03000033c */

  outpw( TEST_MEM_SEL_WH, 0x0000 );    /* DEC_TEST_RAM_SEL ... 0x03000768 */

  outpw( TEST_POINT_SEL_WH, 0x0000 );  /* ENC_TEST_POINT_SEL ... 0x03000760 */

  outp( DEM_DSP_RESET_WB, 1);             /* DEM_DSP_RESET ... 0x0300005c */

  outp( AGC_TEST_CTL_WB, 0x00 );       /* CAGC_TEST_CNTL ... 0x03000188 */

  outp( UART_IRDA_WB, 0x00 );          /* MSMU_IRDA ... 0x030007e4 */

  outp( DEM_CTL_WB, 0x00 );            /* DEM_CTL_WB ... 0x03000154 */

  outp( BTF_CTL_WB, 0x00 );            /* BTF_CTL_WB ... 0x030002b4 */

  outp( DFM_VOC_INTF_CONFIG_WB, 0x00); /* DFM_VOC_INTF_CFG ... 0x03000538 */

  outp( DFM_RXWBD_WR_WB, 0x00 );       /* DFM_RX_WBD_WR ... 0x0300056c */

  outp ( SLEEP_CTL_WB, 0x00 );        /* SLEEP_CTL_WB ... 0x03000600 */

#ifdef TIMETEST
  outpw ( TIMETEST_PORT, 0x0000 );
#endif

  //outpw( PS_HOLD_TSEN_R, PS_HOLD_BIT_V );
  outpw( PS_HOLD_TSEN_R, 0x2 );
  //outpw( PS_HOLD_GPIO_R, PS_HOLD_BIT_V );
  outpw( PS_HOLD_GPIO_R, 0x2 );
/*--------------------------------------------------------------------------*/
/* Initialize MSM Interrupt Registers                                       */
/*--------------------------------------------------------------------------*/
  /* Disable interrupts  */
  outpw( DMOD_INT_MASK_0, 0x0000 );
  outpw( DMOD_INT_MASK_1, 0x0000 );

  /* Clear interrupts    */
  outpw( DMOD_INT_CLEAR_0, 0xffff );
  outpw( DMOD_INT_CLEAR_1, 0xffff );

  /* Disable GROUP interrupts */
  outpw ( GPIO_INT_MASK_0, 0x0000 );
  outpw ( GPIO_INT_MASK_1, 0x0000 );
  outpw ( GPIO_INT_MASK_2, 0x0000 );
  outpw ( GPIO_INT_MASK_3, 0x0000 );

  /* Clear GROUP interrupts */
  //outpw ( GPIO_INT_CLEAR_0, GPIO_INT_CLEAR_0_WH_MASK );
  //outpw ( GPIO_INT_CLEAR_1, GPIO_INT_CLEAR_1_WH_MASK );
  //outpw ( GPIO_INT_CLEAR_2, GPIO_INT_CLEAR_2_WH_MASK );
  //outpw ( GPIO_INT_CLEAR_3, GPIO_INT_CLEAR_3_WH_MASK );
  outpw ( GPIO_INT_CLEAR_0, 0xffff );
  outpw ( GPIO_INT_CLEAR_1, 0xffff);
  outpw ( GPIO_INT_CLEAR_2, 0xffff);
  outpw ( GPIO_INT_CLEAR_3, 0xffff );
/*--------------------------------------------------------------------------*/
/* Initialize VREG and PAD Registers                                        */
/*--------------------------------------------------------------------------*/

  /* Set VREG to default values.
  ** NOTE: This is optional if using default values.
  */
  //outp ( VREG_CTL_WB, VREG_CTL_WB__CNTLX_MASK);
  outp ( VREG_CTL_WB, 0x1);

  /* Set Pad strength to default values.
  ** NOTE: This is optional if using default values.
  */
  outp ( PAD_CTL_WB, 0x1 );
#ifdef T_IO_CARD
  outp ( PAD_CTL_WB, PAD_CTL_WB__HDRIVE_CX8FMCLK_MASK );
#endif //T_IO_CARD

}

void
boot_mem_ctrl_init()
{
  /* Test RAM control -- Exit test modes
  */
}


/*===========================================================================

  FUNCTION boot_hw_powerdown()

  DESCRIPTION
    This function clears the PS hold bits to allow phone power off.

  PARAMETERS
    None.

  DEPENDENCIES
    None.
    
  RETURN VALUE
    None.

  SIDE EFFECTS
    None.

===========================================================================*/
void
boot_hw_powerdown()
{

  /* Now clear the GPIO that's attached to the power supply hold-on
     control line.  This allows the phone to power off.  Unfortunately
     this line is in different places for various phone designs.  We
     just clear them all, ignoring any side effects. */
   outpw( PS_HOLD_TSEN_R, PS_HOLD_BIT_V );
   outpw( PS_HOLD_GPIO_R, PS_HOLD_OFF_V );

  for (;;)
     {
      /*---------------------------------------------------------------------
      ** Do nothing until the phone powers off. Make certain the watchdog
      ** does not expire and reset us before the power off.
      **--------------------------------------------------------------------*/
      BOOTHW_KICK_WATCHDOG();

     }
}

/*===========================================================================

  FUNCTION boot_hw_tlmm_shadow()

  DESCRIPTION
        This function initializes each register that needs to be 
    initialized to enable several gpios to a specific mode.

        This function uses MSM_OUTHM/ASB_OUTHM macro to keep a shadow of 
    the registers written. MSM_OUTHM/ASB_OUTHM macro calls functions within 
    (rex_int_lock() & rex_int_free()). As a result, this function uses the 
    stack which is undesirable within the boot code. Use this function for 
    external code and not within the boot code.
    
  PARAMETERS
    None.
    
  DEPENDENCIES
    None.
        
  RETURN VALUE
    None.    

  SIDE EFFECTS
    It uses the stack

===========================================================================*/
//void boot_hw_tlmm_shadow(void)
//{
// register word counter = 0;

//  while(GpioFuncSelInit[counter].addr != NULL)
//  {
//    if (GpioFuncSelInit[counter].addr <  ASB_BASE)
//    {
//        MSM_OUTHM(GpioFuncSelInit[counter].addr, 0xffff, GpioFuncSelInit[counter].val);
//    }
//    else
//    {
//        ASB_OUTHM(GpioFuncSelInit[counter].addr, 0xffff, GpioFuncSelInit[counter].val);
//    }
//    counter++; 
//  }
  
//}

/*===========================================================================

  FUNCTION boot_hw_mem_wt_st_cfg()

  DESCRIPTION
    Setup MSM510X memory wait states. 

  PARAMETERS
    None.

  DEPENDENCIES
    None.
       
  RETURN VALUE
    None.

  SIDE EFFECTS
    None.

===========================================================================*/
void boot_hw_mem_wt_st_cfg(void)
{
  //BOOT_HW_SET_WAIT_STATES_TCXO();
}