boothw_6000.c

在高通的手机平台下,一个下载手机.bin文件到手机的flash中的工具,包含PC端的程序代码和运行在基带处理器中的代码.

/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*

                  B O O T  H A R D W A R E  I N I T I A L I Z A T I O N

GENERAL DESCRIPTION
  This module initializes MSM memory and peripheral control hardware to enable
  access to the entire target ROM and RAM address space.

EXTERNALIZED FUNCTIONS
  boot_hw_ctrl_init()
    Initialize MSM hardware and peripherals.


Copyright (c) 1991,1992,1995,1996,1997,1998,1999 by QUALCOMM Incorporated.
Copyright (c) 2000,2001,2002 by QUALCOMM Incorporated.
All Rights Reserved.
*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
//
/*===========================================================================

                           EDIT HISTORY FOR FILE
  This section contains comments describing changes made to the module.
  Notice that changes are listed in reverse chronological order.

$Header:   L:/src/asw/MSM6000/vcs/boothw_6000.c_v   1.5   22 Mar 2002 08:33:06   clang  $

when       who     what, where, why
--------   ---     ----------------------------------------------------------
12/26/05  wufei.lin creat file for msm6000_bt
--------   ---     ----------------------------------------------------------
03/21/02   bgc/cml Added FFA support to boot_hw_ctrl_init.
03/11/02   rmd     Featurized the sleep clock under FEATURE_PMIC_32K_XTAL.
01/25/02   cml     Added conditional include for pm.h
01/04/02   rmd     Added support for the PM60X0 32 KHZ external crystal 
                   (PMIC_HAS_32K_XTAL).
02/12/01   rmd     Removed clock switching code. Clock switching code is now initialized
                   in clock regime.
01/08/01   rmd     Modified boot_hw_ctrl_init so it checks the clock source before doing any
                   clock switching.
12/20/00   rmd     Added !DEBUG_ICE_MODE around UP_CLK_CTL0 clock switching.
12/18/00   rmd     Changed boot_hw_ctl_init so that MCLK is set to TCXO during
                   boot up.
12/12/00   djd     Change name from boothw_5105.c to boothw_6000.c
12/04/00   djd     Changed DEBUG_IO_CARD to T_IO_CARD.
11/27/00   rmd     Moved MSM_WAIT and ASB_DECODE cycle initialization to the beginning 
                   of boot code.
11/21/00   rmd     Moved to the clk regime code, the initialization of: 
                   MSM_CLK_CTL6_WH, CDMA MND counter and GPS MND counter.
11/13/00   rmd     Changed the number of MSM registers wait states to 0.
11/10/00   rmd     Modified boot_hw_tlmm_shadow() and boot_hw_chipxn_clk_init()
                   so that they contain all the initialization necessary 
                   without the need of any extra code.
11/09/00   rmd     Replaced hard coded shift values with SHIFT_FROM_MASK(BIT MASK) so
                   that register bits get shifted depending on the bit mask defined in
                   msmXXXXreg.h.
11/03/00   rmd     Removed write to MOD_CLK_CTL. We initialize this register in
                   enc_init().
11/01/00   rmd     Included bsp.h which has flags that are needed in boothwi_5105.h.
                   Replaced FEATURE_TXCO19XX with 
                   (BSP_OSCILLATOR_IN == BSP_TCXO_19PXX_MHZ).
10/16/00   rmd     Renamed this file boothw_MSM5105.c to show that this is a MSM5105 
                   hardware dependent file.                   
                   Created boot_hw_chipxn_clk_init(), boot_hw_tlmm_shadow() and 
                   boot_hw _mem_wt_st_cfg(). These functions contain shared code between
                   the boot code and other modules. 
10/11/00   et      wrote to the PAD_CTL_WB__HDRIVE_CX8FMCLK_MASK bit in order to drive 
                   the CX8 strength to high
10/09/00   rmd     Moved initialization code from boot_hw_tlmm_init() to macros
                   in boothw.h so that it can be shared with other modules.
09/19/00   rm      Merged changes to support Digital Io card. 
09/08/00   rmd     Made changes to boot_hw_ctrl_int and boot_hw_tlmm_init to
                   support the MSM5105.
08/28/00   rmd     Moved KICK_WATCHDOG to boothw.h, renamed it BOOTHW_KICK_WATCHDOG.
07/12/00   jc      Corrected support for MSM3300 to ifdef T_MSM33.
06/30/00   jc      Removed FEATURE_SURF3100 from PS_HOLD assertion and timetest
                   port initialization.  Added support for T_MSM33 since
                   SDAC_ENABLE is only available on msm3100 (not msm3300).
04/25/00   mk/jc   Added support for FEATURE_TCXO1980 and initialization of
                   MSM_CLK_CTL6 to init the MN counter clock sources to default
                   values. ( needed for WDOG timeout )
04/02/00   sm      Added FEATURE_STEREO_DAC support.
01/20/00   jc      Added support for FEATURE_PM1000_32K_XTAL
01/06/99   mk      Added FEATURE_TCXO1920 support.
12/08/99   mk      Changed sleep_clk _CTL4 settings.
11/03/99   mk      Added VREG, PAD and TIMETEST_PORT initialization.
10/28/99   jc      Initialized GPIO GROUP interrupts.
10/04/99   mk      Changed to support MSM3100 family ASICs only.
09/16/99   mk      Introduced FEATURE_SURF3100.
09/16/99   mk      Deleted obsolete PRODUCTION_SURF2000_xxx based code.
09/02/99   mk      Updated for MSM3100 REV2.
08/20/99   mk      ARM2.5 compiler update.
08/02/99   jc      Added TLMM functions for gpio function sel registers 0,1.
07/15/99   mk/jc   Added -bsp- version of CS/WS init, new MSM3100 clock init
                   and ASB_DECODE_CTL=1WS, undefined SBI init loop via T_MSM31.
06/15/99   spf     Added 10/20MHz TCXO clock featurization.
05/12/99   mk      Added initial MSM3100 support.
04/09/99   ms      Lint cleanup.
03/31/99   ms      Disabled dead cycle to improve performance.
                   This removes 1 clock on memory write.
                   Split up pause timer delay to fit the time in 12 bit int.
03/25/99   ms      Kicking watchdog during powerdown to ensure that the
                   watchdog does not reset the phone and trash the powerdown.
02/08/99   jc      Removed conditional compile around set of UP_CLK_CTL1.
12/11/98   udp     Added comments for KHZ/MHZ and updated CS_CTL_WH to disable
                   External Bus debug for MSM accesses
12/10/98   dnn     Changed #ifdef FEATURE_SLEEP_32KHZ to FEATURE_SLEEP_SLOW_CLOCK
                   Added support for high frequency [1.92 MHz - 3.84 MHz] sleep clock,
                   using FEATURE_SLEEP_SLOW_CLOCK_1P92_3P84_MHZ
11/17/98   jkl     Initialize Interrupt Registers
10/27/98   rm      Added changes to power up TCXO
09/16/98   udp     Fix typo for FEATURE_SLEEP_32KHZ undef'd
09/14/98   ih,rnc  Added 32kHz sleep support.
           ajn,dnn
09/13/98   hcg     removed boot.h from build.  Added comments/history, etc.
07/26/98   hcg     Revised for coding standard, removed unused code
06/01/98   hcg     Created

===========================================================================*/
//
/*===========================================================================

                     INCLUDE FILES FOR MODULE

===========================================================================*/
//#include "comdef.h"
//#include "processor.h"
//#include "assert.h"             
//#include "msm.h"
//#include "debug.h"
//#include "target.h"
//#include "bsp.h"
//#include "boothw.h"
//#include "boothwi_6000.h"
//#include "clk.h"
//#include "clkregim.h"
//#include "timetest.h"

//#include "boothw_6000.h"



//#include "bsp.h"
//#include "comdef.h"
//#include "msm6000asb.h"


//#include "msm6000io.h"

//;#include "boothwi_6000.h"
//;#include "msm6000bits.h"
//;#include "msm6000reg.h"


#include "boothw_6000_include.h"


#ifdef FEATURE_PMIC
  //#include "pm.h"
#endif /* FEATURE_PMIC */



/*===========================================================================

            LOCAL DEFINITIONS AND DECLARATIONS FOR MODULE

  This section contains local definitions for constants, macros, types,
  variables and other items needed by this module.

===========================================================================*/

/*  This array contains the addr and initial value for each register
    that needs to be initialized to enable several gpios to a specific
    mode*/
    
static const GpioFuncSelType  GpioFuncSelInit[]={BOOT_HW_GPIO_FUNC_SEL_INIT};
//
/*===========================================================================

  FUNCTION boot_hw_ctrl_init()

  DESCRIPTION
    Initializes MSM control registers to enable access to the entire
    target ROM and RAM address space.

  PARAMETERS
    None.

  DEPENDENCIES
    None.

  RETURN VALUE
    None.

  SIDE EFFECTS
    The MSM chip is initialized.
===========================================================================*/
void
boot_hw_ctrl_init()
{
/***********************************************************************************************
 *** Warning: This routine can make no function calls and reference no global data since we  ***
 ***          are still in rom and have no stacks yet.                                       ***
 ***********************************************************************************************/
/*
** ASB Block Initialization
*/
  /* Configure ASB_DECODE_CTL */
  outpw( ASB_DECODE_CTL_WH, ASB_DECODE_CTL_WAIT );
 
  /* Configure MSM_WAIT */
  outpw( MSM_WAIT_WH, MSM_WAIT_WH_0WAIT );
                   
  /* Configure MEMORY_WAIT2 */
  /* Configure MEMORY_WAIT1 */
 // BOOT_HW_SET_WAIT_STATES_TCXO();
   outpw (MEMORY_WAIT1_WH, 0x2023);  
  
   outpw (MEMORY_WAIT2_WH, 0x824);

//#if (ROM2_BASE == 16)
//  outpw( GPIO_INT_ADDR_SEL_WH, GPIO_INT_ADDR_SEL_WH__ADDRESS_21_EN_MASK);
//#elif (ROM2_BASE == 32)

  outpw( GPIO_INT_ADDR_SEL_WH,  GPIO_INT_ADDR_SEL_WH__ADDRESS_21_EN_MASK | 
                                GPIO_INT_ADDR_SEL_WH__ADDRESS_22_EN_MASK );
//#endif /*ROM2_BASE*/
  
  outpw ( BSIZER_CTL1_WH, (ROM1_WR_CNT << SHIFT_FROM_MASK(BSIZER_CTL1_WH__ROM_WR_CNT)) |
                          (ROM1_RD_CNT << SHIFT_FROM_MASK(BSIZER_CTL1_WH__ROM_RD_CNT)) |
                          (ROM2_WR_CNT << SHIFT_FROM_MASK(BSIZER_CTL1_WH__ROM2_WR_CNT)) |
                          (ROM2_RD_CNT << SHIFT_FROM_MASK(BSIZER_CTL1_WH__ROM2_RD_CNT)) );

  /* Configure GP_ACCESS */
  outpw( GP_CS_N_WAIT_WH, (GP2_BASE   << SHIFT_FROM_MASK(GP_CS_N_WAIT_WH__GP2_BASE)) |
                          (GP2_ACCESS << SHIFT_FROM_MASK(GP_CS_N_WAIT_WH__GP2_ACCESS)) |
                          (GP_ACCESS  << SHIFT_FROM_MASK(GP_CS_N_WAIT_WH__GP_WAIT )) );

  /* Configure BSIZER_CTL2 */
  outpw ( BSIZER_CTL2_WH, 0x1012);//(RAM1_BSIZE_EN << SHIFT_FROM_MASK(BSIZER_CTL2_WH__RAM_BSIZE_EN )) |
                          //(RAM2_BSIZE_EN << SHIFT_FROM_MASK(BSIZER_CTL2_WH__PCS6_BSIZE_EN)) |
                          //(RAM1_WR_CNT   << SHIFT_FROM_MASK(BSIZER_CTL2_WH__RAM_WR_CNT)) |
                          //(RAM1_RD_CNT   << SHIFT_FROM_MASK(BSIZER_CTL2_WH__RAM_RD_CNT)) |
                          //(RAM2_WR_CNT   << SHIFT_FROM_MASK(BSIZER_CTL2_WH__PCS6_WR_CNT)) |
                          //(RAM2_RD_CNT   << SHIFT_FROM_MASK(BSIZER_CTL2_WH__PCS6_RD_CNT)) );
  
  /* Configure LCD_CTL */
  outpw( LCD_CTL_WH, (LCD_ACCESS  << SHIFT_FROM_MASK(LCD_CTL_WH__LCD_WAIT)) |
                     (LCD_E_SETUP << SHIFT_FROM_MASK(LCD_CTL_WH__LCD_E_SETUP)) |
                     (LCD_E_HIGH  << SHIFT_FROM_MASK(LCD_CTL_WH__LCD_E_HIGH)) );
  

  /* Configure CS_CTL */
  outpw ( CS_CTL_WH, 0x206);//(BY16SRAM_ONLY << SHIFT_FROM_MASK(CS_CTL_WH__BY16SRAM_ONLY)) |
                    // (GP2_CS_EN     << SHIFT_FROM_MASK(CS_CTL_WH__GP2_CS_EN)) |
                    // (SRAM_PCS6_CFG << SHIFT_FROM_MASK(CS_CTL_WH__SRAM_PCS6_CFG)) |
                     //(GP_CS_EN      << SHIFT_FROM_MASK(CS_CTL_WH__GP_CS_EN)) |
                    // (LCD_E_EN      << SHIFT_FROM_MASK(CS_CTL_WH__LCD_E_EN)) |
                    // (LCD_CS_EN     << SHIFT_FROM_MASK(CS_CTL_WH__LCD_CS_EN)) |
                    // (RAM2_CS_EN    << SHIFT_FROM_MASK(CS_CTL_WH__PCS6_EN)) |
                   // (RAM1_CS_EN    << SHIFT_FROM_MASK(CS_CTL_WH__RAM_CS_EN)) |
                   // (ROM2_CS_EN    << SHIFT_FROM_MASK(CS_CTL_WH__ROM2_CS_EN)) );  
}

/*===========================================================================

  FUNCTION boot_hw_tlmm_init()

  DESCRIPTION
    Initializes MSM control registers to enable access to the entire
    target ROM and RAM address space.

  PARAMETERS
    None.

  DEPENDENCIES
    None.

  RETURN VALUE