msm6000bits.h

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#define ENC_VOC_REF_DIS_M           MOD_CLK_CTL_WH__VOC_REF_DISABLE_MASK

#define ENC_VOC_REF_DIS_V           (0x01 << \
        SHIFT_FROM_MASK(MOD_CLK_CTL_WH__VOC_REF_DISABLE))
        
#define ENC_VOC_REF_ENA_V           (0x00 << \
        SHIFT_FROM_MASK(MOD_CLK_CTL_WH__VOC_REF_DISABLE))

/*      Transmit clocks disable     */        
#define ENC_TX_CLKS_DIS_M           MOD_CLK_CTL_WH__TX_CLKS_DISABLE_MASK     

/*      Transmit clocks disable on  */
#define ENC_TX_CLKS_DIS_V           (0x01 << \
        SHIFT_FROM_MASK(MOD_CLK_CTL_WH__TX_CLKS_DISABLE))
        
/*      Transmit clocks disable off */
#define ENC_TX_CLKS_ENA_V           (0x00 << \
        SHIFT_FROM_MASK(MOD_CLK_CTL_WH__TX_CLKS_DISABLE))
        
/*-   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -*/
/*      Power amplifier control    */
#define ENC_TXP_CTL_M               MOD_MISC_CTL_WH__PA_CTL_MASK

/*      TX_PUNCT off (low)         */
#define ENC_TXP_OFF_V               (0x00 << \
        SHIFT_FROM_MASK(MOD_MISC_CTL_WH__PA_CTL))
        
/*      TX_PUNCT follows MASK_DATA */        
#define ENC_TXP_MASK_V              (0x01 << \
        SHIFT_FROM_MASK(MOD_MISC_CTL_WH__PA_CTL))

/*      TX_PUNCT on (high)         */        
#define ENC_TXP_ON_V                (0x02 << \
        SHIFT_FROM_MASK(MOD_MISC_CTL_WH__PA_CTL))

/*      Access channel transmitted */
#define ENC_ACCESS_M                MOD_MISC_CTL_WH__IS95A_ACCESS_CH_MASK

/*      yes */
#define ENC_ACCESS_V                (0x01 << \
        SHIFT_FROM_MASK(MOD_MISC_CTL_WH__IS95A_ACCESS_CH))

/*      no  */        
#define ENC_NO_ACCESS_V             (0x00 << \
        SHIFT_FROM_MASK(MOD_MISC_CTL_WH__IS95A_ACCESS_CH))

/*      IS95 C Pilot transmitted */
#define ENC_IS95C_PILOT_M           MOD_MISC_CTL_WH__IS95C_PCH_EN_MASK   

/*      yes */
#define ENC_IS95C_PILOT_V           (0x01 << \
        SHIFT_FROM_MASK(MOD_MISC_CTL_WH__IS95C_PCH_EN))

/*      no  */
#define ENC_NO_IS95C_PILOT_V        (0x00 << \
        SHIFT_FROM_MASK(MOD_MISC_CTL_WH__IS95C_PCH_EN))

/*      Test IS95 C PC bits transmitted */
#define ENC_IS95C_PCBIT_M           MOD_MISC_CTL_WH__IS95C_PCBIT_REG_EN_MASK

/*      yes */                                           
#define ENC_IS95C_PCBIT_V           (0x01 << \
        SHIFT_FROM_MASK(MOD_MISC_CTL_WH__IS95C_PCBIT_REG_EN))
        
/*      no  */        
#define ENC_NO_IS95C_PCBIT_V        (0x00 << \
        SHIFT_FROM_MASK(MOD_MISC_CTL_WH__IS95C_PCBIT_REG_EN))
        
/*      no  */                                                                     
#define ENC_ZERO_PCBIT_V            (0x00 << \
        SHIFT_FROM_MASK(MOD_MISC_CTL_WH__IS95C_PCBIT_REG_EN))
                                                                          
/*      TX in offset-bin or 2'c comp */                                                                          
#define ENC_TX_FMT_M                MOD_MISC_CTL_WH__TX_DATA_FORMAT_MASK     

/*      TX in 2's comp               */
#define ENC_TX_2S_V                 (0x01 << \
        SHIFT_FROM_MASK(MOD_MISC_CTL_WH__TX_DATA_FORMAT))
       
/*      TX offset-binary             */
#define ENC_TX_OFF_V                (0x00 << \
        SHIFT_FROM_MASK(MOD_MISC_CTL_WH__TX_DATA_FORMAT))

/*-   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -*/
/*                             TEST REGISTERS                              */
/*-   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -*/

/*      Set IQ Phase Waveform         */
#define ENC_SET_IQ_M                MOD_TEST_CTL_WH__SET_IQ_HIGH_MASK     

/*      I & Q high after spreading    */
#define ENC_SET_IQ_V                (0x01 << \
        SHIFT_FROM_MASK(MOD_TEST_CTL_WH__SET_IQ_HIGH))

/*      Don't force I & Q             */
#define ENC_NO_SET_IQ_V             (0x00 << \
        SHIFT_FROM_MASK(MOD_TEST_CTL_WH__SET_IQ_HIGH))

/*      Internal Master Mask Control  */
#define ENC_MASK_CTL_M              MOD_TEST_CTL_WH__MASK_CTL_MASK     

/*      Set MASK low                  */
#define ENC_MASK_LO_V               (0x00 << \
        SHIFT_FROM_MASK(MOD_TEST_CTL_WH__MASK_CTL))

/*      MASK functions normally       */
#define ENC_MASK_V                  (0x01 << \
        SHIFT_FROM_MASK(MOD_TEST_CTL_WH__MASK_CTL))
                                    
/*      Set MASK high                 */
#define ENC_MASK_HI_V               (0x03 << \
        SHIFT_FROM_MASK(MOD_TEST_CTL_WH__MASK_CTL))

/*      Transmit data control         */
#define ENC_TX_DAT_CTL_M            MOD_TEST_CTL_WH__TX_DATA_CTL_MASK

/*      source = FIR filter           */
#define ENC_TX_FIR_V                (0x00 << \
        SHIFT_FROM_MASK(MOD_TEST_CTL_WH__TX_DATA_CTL))

/*      source = TX_DATA_TEST         */
#define ENC_TX_TEST_V               (0x01 << \
        SHIFT_FROM_MASK(MOD_TEST_CTL_WH__TX_DATA_CTL))

/*      Rx spectral inversion         */
#define ENC_RX_POL_M                MOD_TEST_CTL_WH__RX_SPECTRAL_INVERSION_MASK

/*      Invert                        */
#define ENC_RX_INV_V                (0x01 << \
        SHIFT_FROM_MASK(MOD_TEST_CTL_WH__RX_SPECTRAL_INVERSION))

/*      Normal                        */
#define ENC_RX_NORM_V               (0x00 << \
        SHIFT_FROM_MASK(MOD_TEST_CTL_WH__RX_SPECTRAL_INVERSION))

/*      Tx spectral inversion         */        
#define ENC_TX_POL_M                MOD_TEST_CTL_WH__TX_SPECTRAL_INVERSION_MASK

/*      Invert                        */
#define ENC_TX_INV_V                (0x01 << \
        SHIFT_FROM_MASK(MOD_TEST_CTL_WH__TX_SPECTRAL_INVERSION))

/*      Normal                        */
#define ENC_TX_NORM_V               (0x00 << \
        SHIFT_FROM_MASK(MOD_TEST_CTL_WH__TX_SPECTRAL_INVERSION))
        
/*-   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -*/

#define ENC_GATING_MODE_M           (MOD_MISC_CTL_WH__FCH_EIGHTH_GATE_MASK | \
                                     MOD_MISC_CTL_WH__PILOT_GATE_MASK | \
                                     MOD_MISC_CTL_WH__HHO_PRMBL_MASK)
                                     
#define ENC_DCCH_EN_M               MOD_MISC_CTL_WH__IS95C_DCCH_EN_MASK
#define ENC_DCCH_EN_V               (0x01 << \
        SHIFT_FROM_MASK(MOD_MISC_CTL_WH__IS95C_DCCH_EN))
        
#define ENC_DCCH_DIS_V              (0x00 << \
        SHIFT_FROM_MASK(MOD_MISC_CTL_WH__IS95C_DCCH_EN_MASK))       

/* AGC_CTL8 MASK_DELAY bit definitions */        
#define AGC_CTL8_WB__MASK_DELAY_1PCG (0x00 << \
        SHIFT_FROM_MASK(AGC_CTL8_WB__MASK_DELAY))
        
#define AGC_CTL8_WB__MASK_DELAY_2PCG (0x01 << \
        SHIFT_FROM_MASK(AGC_CTL8_WB__MASK_DELAY))
        
#define AGC_CTL8_WB__MASK_DELAY_3PCG (0x02 << \
        SHIFT_FROM_MASK(AGC_CTL8_WB__MASK_DELAY))
        
#define AGC_CTL8_WB__MASK_DELAY_4PCG (0x03 << \
        SHIFT_FROM_MASK(AGC_CTL8_WB__MASK_DELAY))                        
        
#define AGC_CTL8_WB__MASK_DELAY_5PCG (0x04 << \
        SHIFT_FROM_MASK(AGC_CTL8_WB__MASK_DELAY))
        
#define AGC_CTL8_WB__MASK_DELAY_6PCG (0x05 << \
        SHIFT_FROM_MASK(AGC_CTL8_WB__MASK_DELAY))
        
#define AGC_CTL8_WB__MASK_DELAY_7PCG (0x06 << \
        SHIFT_FROM_MASK(AGC_CTL8_WB__MASK_DELAY))
        
#define AGC_CTL8_WB__MASK_DELAY_8PCG (0x07 << \
        SHIFT_FROM_MASK(AGC_CTL8_WB__MASK_DELAY))        
        
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//
//               HW CODE BITS DEFINITIONS
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------

/* MDR Supplemental Channel Frame Sync Control enable/disable */
#define DEM_FRAME_OFF_WB__SUP_SYNC_BYPASS_ENA           (1 << \
        SHIFT_FROM_MASK(DEM_FRAME_CTL_WB__FRAME_SYNC_BYPASS))

#define DEM_FRAME_OFF_WB__SUP_SYNC_BYPASS_DIS           (0 << \
        SHIFT_FROM_MASK(DEM_FRAME_CTL_WB__FRAME_SYNC_BYPASS))

#define UART2_CR__TX_DIS                                (1 << \
        SHIFT_FROM_MASK(UART2_CR_WB__UART_TX_DISABLE))

#define UART2_CR__RX_DIS                                (1 << \
        SHIFT_FROM_MASK(UART2_CR_WB__UART_RX_DISABLE))
 
#define CODEC_CTL_WH__UART2_SEL_DIS                     (0 << \
        SHIFT_FROM_MASK(CODEC_CTL_WH__UART2_SEL))

#define CODEC_CTL_WH__UART2_SEL_ENA                     (1 << \
        SHIFT_FROM_MASK(CODEC_CTL_WH__UART2_SEL))


//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//
//                DLOAD CODE BITS DEFINITIONS
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------

/*      Automatic RFR control         */
#define UART_MR1_RFRC               (0x01 << \
        SHIFT_FROM_MASK(UART_MR1_WB__RX_RDY_CTL))

/*      Automatic CTS control         */
#define UART_MR1_CTSC               (0x01 << \
        SHIFT_FROM_MASK(UART_MR1_WB__CTS_CTL))

/*      8 bits per character          */
#define UART_MR2_8BPC               (0x03 << \
        SHIFT_FROM_MASK(UART_MR2_WB__BITS_PER_CHAR))

/*      1 stop bit                    */
#define UART_MR2_1SB                (0x01 << \
        SHIFT_FROM_MASK(UART_MR2_WB__STOP_BIT_LEN))

/*      Hunt character received       */
#define UART_SR_HUNT_RXD            (0x01 << \
        SHIFT_FROM_MASK(UART_SR_RB__HUNT_CHAR))

/*      Break received                */
#define UART_SR_BREAK_RXD           (0x01 << \
        SHIFT_FROM_MASK(UART_SR_RB__RX_BREAK))

/*      Parity or Framing error       */
#define UART_SR_PF_ERR              (0x01 << \
        SHIFT_FROM_MASK(UART_SR_RB__PAR_FRAME_ERR))

/*      Overrun error                 */
#define UART_SR_OVR_ERR             (0x01 << \
        SHIFT_FROM_MASK(UART_SR_RB__UART_OVERRUN))

/*      Transmitter empty             */
#define UART_SR_TXEMT               (0x01 << \
        SHIFT_FROM_MASK(UART_SR_RB__TXEMT))

/*      Transmitter ready             */
#define UART_SR_TXRDY               (0x01 << \
        SHIFT_FROM_MASK(UART_SR_RB__TXRDY))

/*      Receiver full                 */
#define UART_SR_RXFULL              (0x01 << \
        SHIFT_FROM_MASK(UART_SR_RB__RXFULL))

/*      Receiver ready                */
#define UART_SR_RXRDY               (0x01 << \
        SHIFT_FROM_MASK(UART_SR_RB__RXRDY))

/*      Reset error status            */                                            
#define UART_CR_RESET_ERR           (0x03 << \
        SHIFT_FROM_MASK(UART_CR_WB__CHANNEL_COMMAND))

/*      Reset transmitter             */
#define UART_CR_RESET_TX            (0x02 << \
        SHIFT_FROM_MASK(UART_CR_WB__CHANNEL_COMMAND))
        
/*      Reset receiver                */
#define UART_CR_RESET_RX            (0x01 << \
        SHIFT_FROM_MASK(UART_CR_WB__CHANNEL_COMMAND))
        
/*      Enable receiver               */
#define UART_CR_RX_ENA              (0x01 << \
        SHIFT_FROM_MASK(UART_CR_WB__UART_RX_EN))

/*      Enable transmitter            */
#define UART_CR_TX_ENA              (0x01 << \
        SHIFT_FROM_MASK(UART_CR_WB__UART_TX_EN))
         
/*      Tx FIFO at or below the mark  */         
#define UART_ISR_TXLEV              (0x01 << \
        SHIFT_FROM_MASK(UART_ISR_RB__TXLEV))
        
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//
//                DEMOD CODE BITS DEFINITIONS
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------

#define DEM_FIRMWARE_START_DOWNLOAD (0x00 << \
        SHIFT_FROM_MASK(DEM_DSP_RESET_WB__FIRMWARE_START))
        
#define DEM_FIRMWARE_END_DOWNLOAD   (0x01 << \
        SHIFT_FROM_MASK(DEM_DSP_RESET_WB__FIRMWARE_START))



#endif /*MSM6000BITS_H*/