msm6000bits.h

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#define MSM_CLK_CTL7_WH__CODEC_CLK_SEL_PLLOUT_DIV96     (5 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__CODEC_CLK_SEL))
#define MSM_CLK_CTL7_WH__CODEC_CLK_SEL_TCXO_DIV4         (6 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__CODEC_CLK_SEL))
#define MSM_CLK_CTL7_WH__CODEC_CLK_SEL_TCXO_DIV8         (7 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__CODEC_CLK_SEL))
#define MSM_CLK_CTL7_WH__CODEC_CLK_SEL_TCXO_DIV16        (8 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__CODEC_CLK_SEL))
#define MSM_CLK_CTL7_WH__CODEC_CLK_SEL_SLEEP_SHMITT_OUT  (9 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__CODEC_CLK_SEL))
/*--------------------------------------------------------------------------*/
//      Bit [8] Reserved
  
/*--------------------------------------------------------------------------*/
//      Bit [10:9] RXDSP_CLK_SEL, defines the clock source for Super Finger DSP
//      and Viterbi Decoder.

#define MSM_CLK_CTL7_WH__CDMA_RXDSP_CLK_SEL_CHIPX8              (0x00 <<\
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__CDMA_RXDSP_CLK_SEL))
        
#define MSM_CLK_CTL7_WH__RXDSP_CLK_SEL_TCXO_PIN            (0x01 <<\
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__RXDSP_CLK_SEL))
        
#define MSM_CLK_CTL7_WH__CDMA_RXDSP_CLK_SEL_CHIPX16             (0x02 <<\
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__CDMA_RXDSP_CLK_SEL))
        
#define MSM_CLK_CTL7_WH__CDMA_RXDSP_CLK_SEL_GPIO28              (0x03 <<\
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__CDMA_RXDSP_CLK_SEL))

/*--------------------------------------------------------------------------*/
//      Bit [13:12] UART_CLK_SEL, defines the clock source for UARTs.
/*      TCXO/4 */
#define MSM_CLK_CTL7_WH__UART_CLK_SEL_TCXO4             (0 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__UART_CLK_SEL))

/*      SLEEP Xtal */
#define MSM_CLK_CTL7_WH__UART_CLK_SEL_SLEEP_XTAL        (1 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__UART_CLK_SEL))

#define MSM_CLK_CTL7_WH__UART_CLK_SEL_TCXO              (2 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__UART_CLK_SEL))

#define MSM_CLK_CTL7_WH__UART_CLK_SEL_PDM1              (3 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__UART_CLK_SEL))

/*--------------------------------------------------------------------------*/
//      Bit [15:14] CDMA_CHIP_TEST_CLK_SEL, select chipx16(19.6608MHz) for a
//      variety of sources.
#define MSM_CLK_CTL7_WH__CDMA_CLK_SEL_PLLOUT_DIV5             (0 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__CDMA_CHIP_TEST_CLK_SEL))

#define MSM_CLK_CTL7_WH__CDMA_CLK_SEL_PLLOUT_DIV2_5           (1 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__CDMA_CHIP_TEST_CLK_SEL))

#define MSM_CLK_CTL7_WH__CDMA_CLK_SEL_TCXO                    (2 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__CDMA_CHIP_TEST_CLK_SEL))

#define MSM_CLK_CTL7_WH__CDMA_CLK_SEL_GPIO28                  (3 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__CDMA_CHIP_TEST_CLK_SEL))


/*----------------------------------------------------------------------------
  MSM CLK Control 8
----------------------------------------------------------------------------*/
/*-------------------------------------------------------------------------*/
//      Bits [0] Reserved

/*-------------------------------------------------------------------------*/
//      Bits [1] DIV5_EN, enable the divide-by-5 in the analog clock generator.
#define MSM_CLK_CTL8_WH__DIV5_DIS                        (0U << \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__DIV5_EN)) 
#define MSM_CLK_CTL8_WH__DIV5_ENA                        (1U << \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__DIV5_EN)) 

/*-------------------------------------------------------------------------*/
//      Bits [2] RX_GMC_CLK_DIFF_SEL, chooses between low-swing differetial
//      transmissio of full-swing single-ended transmission of the rx_gmc_clk
//      signal.
#define MSM_CLK_CTL8_WH__RX_GMC_CLK_DIFF_SEL_SINGLE_END    (0U << \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_GMC_CLK_DIFF_SEL))
#define MSM_CLK_CTL8_WH__RX_GMC_CLK_DIFF_SEL_DIFF          (1U << \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_GMC_CLK_DIFF_SEL))

/*-------------------------------------------------------------------------*/
//      Bits [3] RX_SAMP_CLK_SEL2,
//      1: GPIO50 External source for RX_SAMP_CLK in test mode
//      0: Select clock source based on bits [9:8] (Default)
//      Note: Setting this bit overrides values in bits[9:8] of this
//      register (RX_SAMP_CLK_SEL).
#define MSM_CLK_CTL8_WH__RX_SAMP_CLK_SEL2_EXTERNAL         (1U << \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_SAMP_CLK_SEL2))
#define MSM_CLK_CTL8_WH__RX_SAMP_CLK_SEL2_INTERNAL         (0U << \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_SAMP_CLK_SEL2))

/*-------------------------------------------------------------------------*/
//      Bits [4] DIV2_5_EN, disables the DIV12.5 circuitry when not used.
#define MSM_CLK_CTL8_WH__DIV2_5_DIS                        (0U << \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__DIV2_5_EN)) 
#define MSM_CLK_CTL8_WH__DIV2_5_ENA                        (1U << \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__DIV2_5_EN)) 

/*-------------------------------------------------------------------------*/
//      Bits [5] RX_MOD_CLK_DIFF_SEL, chooses between low-swing differetial
//      transmissio of full-swing single-ended transmission of the rx_mod_clk
//      signal.
#define MSM_CLK_CTL8_WH__RX_MOD_CLK_DIFF_SEL_SINGLE_END    (0U << \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_MOD_CLK_DIFF_SEL))
#define MSM_CLK_CTL8_WH__RX_MOD_CLK_DIFF_SEL_DIFF          (1U << \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_MOD_CLK_DIFF_SEL))

/*-------------------------------------------------------------------------*/
//      Bits [6] RX_GMC_CLK_EN, enables the rx_gmc_clk signal going to the 
//      analog block.
#define MSM_CLK_CTL8_WH__RX_GMC_CLK_DIS                 (0U << \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_GMC_CLK_EN))
#define MSM_CLK_CTL8_WH__RX_GMC_CLK_ENA                 (1U << \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_GMC_CLK_EN))

/*-------------------------------------------------------------------------*/
//      Bits [7] RX_MOD_CLK_EN, enables the rx_gmc_clk signal going to the 
//      analog block.
#define MSM_CLK_CTL8_WH__RX_MOD_CLK_DIS                 (0U << \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_MOD_CLK_EN))
#define MSM_CLK_CTL8_WH__RX_MOD_CLK_ENA                 (1U << \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_MOD_CLK_EN))

/*-------------------------------------------------------------------------*/
//      Bits [9:8] RX_SAMP_CLK_SRC_SEL, selects the clock source for 
//      the Rx Sample clock.
#define MSM_CLK_CTL8_WH__RX_SAMP_CLK_SEL_TCXO           (0U <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_SAMP_CLK_SEL))

        /* CDMA */
#define MSM_CLK_CTL8_WH__RX_SAMP_CLK_SEL_CDMA_CX16      (1U <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_SAMP_CLK_SEL))

        /* AMPS ZIF */
#define MSM_CLK_CTL8_WH__RX_SAMP_CLK_SEL_TCXO_DIV2      (2U <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_SAMP_CLK_SEL))

        /* AMPS SuperHet */
#define MSM_CLK_CTL8_WH__RX_SAMP_CLK_SEL_TCXO_DIV4      (3U <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_SAMP_CLK_SEL))

/*-------------------------------------------------------------------------*/
//      Bits [13:11]  Analog clock source selection.
//      
  /* tcxo/2 */
#define MSM_CLK_CTL8_WH__RX_GMC_CLK_SRC_SEL_TCXO2         (0U <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_GMC_CLK_SRC_SEL))
  /* tcxo/4 */
#define MSM_CLK_CTL8_WH__RX_GMC_CLK_SRC_SEL_TCXO4         (1U <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_GMC_CLK_SRC_SEL))
  /* pllout/5 */
#define MSM_CLK_CTL8_WH__RX_GMC_CLK_SRC_SEL_DIV5          (4U <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_GMC_CLK_SRC_SEL))
  /* pllout/12.5 */
#define MSM_CLK_CTL8_WH__RX_GMC_CLK_SEL_TCXO_DIV2_5      (5U <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_GMC_CLK_SEL))
  /* gpio50 */
#define MSM_CLK_CTL8_WH__RX_GMC_CLK_SEL_GPIO50           (6U <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_GMC_CLK_SRC_SEL))

/*-------------------------------------------------------------------------*/
//      Bits [15:14] RX_FRONT_CLK_SRC_SEL, selects the clock source for 
//      the Rx front end (baseband filter, DVGA, etc)
#define MSM_CLK_CTL8_WH__RX_FRONT_CLK_SEL_TCXO           (0U <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_FRONT_CLK_SEL))

        /* CDMA */                                                     
#define MSM_CLK_CTL8_WH__RX_FRONT_CLK_SEL_CDMA_CX16      (1U <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_FRONT_CLK_SEL))

        /* DFM */         
#define MSM_CLK_CTL8_WH__RX_FRONT_CLK_SEL_DFM_720K       (2U <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL8_WH__RX_FRONT_CLK_SEL))


//----------------------------------------------------------------------------
//                         PS_HOLD BIT
// There is a register which contains the control for the GPIO bit which
// sets the hold for the voltage regulators to keep the phone from being
// powered-off.  During boot, the other bits in the register can be left
// as inputs.
//----------------------------------------------------------------------------

#define PS_HOLD_BIT_V               0x0002          //GPIO Bit mask
#define PS_HOLD_OFF_V               0x0000          //GPIO PS_HOLD "off" value

//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//
//               DECODER CODE BITS DEFINITIONS
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------

#define DEINT_CLK_SEL_CHIPX8        (0x00 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__DEC_CLK_SEL))
        
#define DEINT_CLK_SEL_TCXO          (0x01 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__DEC_CLK_SEL))

//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//
//               ENCODER CODE BITS DEFINITIONS
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------

/*---------------------------------------------------------------------------
                          Write Registers
----------------------------------------------------------------------------*/

#define ENC_U_PN_M                  U_PN_STATE_5_WB__U_PN_STATE_41_40_MASK
  /*    Mask to get/set bozo bit ENC_U_PN_S5 */
#define ENC_BOZO_M                  U_PN_STATE_5_WB__BOZO_MASK
        
#define ENC_BOZO_V                  (0x01 << \
        SHIFT_FROM_MASK(U_PN_STATE_5_WB__BOZO))
        
#define ENC_NO_BOZO_V               (0x00 << \
        SHIFT_FROM_MASK(U_PN_STATE_5_WB__BOZO))

/*-   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -*/

/*      data rate mask */
#define ENC_FCH_DATA_RATE_M         FCH_CTL_WH__FCH_ENC_RATE_MASK
/*      rate set mask */
#define ENC_RATE_SET_M              FCH_CTL_WH__FCH_ENC_RATE_SET_MASK
/*      code rate mask */
#define ENC_FCH_CODE_RATE_M         FCH_CTL_WH__FCH_CODE_RATE_MASK

#define ENC_PCH_GAIN_M              MOD_PCH_GAIN_WB__PCH_GAIN_MASK
#define ENC_SCH_GAIN_M              MOD_SCH_FCH_GAIN_WH__SCH_GAIN_MASK
#define ENC_FCH_GAIN_M              MOD_SCH_FCH_GAIN_WH__FCH_GAIN_MASK

#define ENC_TX_VERY_EARLY_FRAME_ADV_M    TX_VERY_EARLY_FRAME_CTL_WH__VERY_EARLY_FRAME_ADV_MASK
#define ENC_TX_VERY_EARLY_FRAME_PRIOD_M  TX_VERY_EARLY_FRAME_CTL_WH__VERY_EARLY_FRAME_PER_MASK
   
#define ENC_IS95_MODE_M             FCH_CTL_WH__IS_95_C_MASK
#define ENC_IS95_C_V                (0x01 << \
        SHIFT_FROM_MASK(FCH_CTL_WH__IS_95_C))
        
#define ENC_IS95_A_V                (0x00 << \
        SHIFT_FROM_MASK(FCH_CTL_WH__IS_95_C))

#define ENC_IS95_FCH_ON_M           FCH_CTL_WH__IS95C_FCH_EN_MASK
#define ENC_IS95C_FCH_ON_V          (0x01 << \
        SHIFT_FROM_MASK(FCH_CTL_WH__IS95C_FCH_EN))
        
#define ENC_IS95C_FCH_OFF_V         (0x00 << \
        SHIFT_FROM_MASK(FCH_CTL_WH__IS95C_FCH_EN))

#define ENC_PCH_M                   MOD_MISC_CTL_WH__IS95C_PCH_EN_MASK
#define ENC_PCH_ON_V                (0x01 << \
        SHIFT_FROM_MASK(MOD_MISC_CTL_WH__IS95C_PCH_EN))
        
#define ENC_PCH_OFF_V               (0x00 << \
        SHIFT_FROM_MASK(MOD_MISC_CTL_WH__IS95C_PCH_EN))

#define ENC_NO_MOD_ROTATION_V       0x0000
#define ENC_FCH_CTL_DIS_V           0x0000
#define ENC_SCH_CTL_DIS_V           0x0000
#define ENC_ZERO_GAIN_V             0x0000
#define ENC_CLEAR_CRC_POLY_V        0x0000
#define ENC_SCH_LTU_SIZE_ZERO_V     0x0000
#define ENC_PUNC_PATTERN_NONE_V     0x0000


#ifdef MSMHW_TURBO_CODING
#error code not present
#endif /* MSMHW_TURBO_CODING */

/*      These values correspond to the MSM5105 documentation*/
#define ENC_SCH_0080_PUNC_PATT      0x0080  // 1/9 puncturing rate
#define ENC_SCH_0800_PUNC_PATT      0x0800  // 1/5 puncturing rate

/*      CRC Length; 0 means disable */
#define ENC_FCH_CRCLEN_M            FCH_CTL_WH__FCH_CRC_LENGTH_MASK  


#define ENC_CRCDIS_V                0x00    /* Don't Generate and insert CRC */

/*-   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -*/
/*      Codec Control */
#define ENC_CODEC_CTL_M             MOD_CLK_CTL_WH__CODEC_CTL_MASK
/*      CODEC_CLK and CODEC_SYNC low    */

#define ENC_CODEC_LO_V              (0x00 << \
        SHIFT_FROM_MASK(MOD_CLK_CTL_WH__CODEC_CTL))
        
/*      CODEC_CLK low, CODEC_SYNC hi    */
#define ENC_CODEC_LOHI_V            (0x01 << \
        SHIFT_FROM_MASK(MOD_CLK_CTL_WH__CODEC_CTL))
        
/*      CODEC_CLK hi, CODEC_SYNC low    */        
#define ENC_CODEC_HILO_V            (0x02 << \
        SHIFT_FROM_MASK(MOD_CLK_CTL_WH__CODEC_CTL))
        
/*      CODEC_CLK and CODEC_SYNC high   */        
#define ENC_CODEC_HI_V              (0x03 << \
        SHIFT_FROM_MASK(MOD_CLK_CTL_WH__CODEC_CTL))
        
/*      CODEC_CLK and CODEC_SYNC normal */        
#define ENC_CODEC_NORM_V            (0x04 << \
        SHIFT_FROM_MASK(MOD_CLK_CTL_WH__CODEC_CTL))

/*      Vocoder frame reference disable - if set, SET VOC_FR_REF, VOC_CS_B,
        VOC_WR_B, VOC_OE_B low */