msm6000bits.h

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/*--------------------------------------------------------------------------*/
//      Bit [0] POWER_DOWN, entry into powerdown by two successive writes of a 1
//      followed by a 0
#define UP_CLK_CTL1_WB__POWER_DOWN_DIS                  (0x00  <<  \
        SHIFT_FROM_MASK(UP_CLK_CTL1_WB__POWER_DOWN))
        
#define UP_CLK_CTL1_WB__POWER_DOWN_EN1                  (0x01  <<  \
        SHIFT_FROM_MASK(UP_CLK_CTL1_WB__POWER_DOWN))
        
#define UP_CLK_CTL1_WB__POWER_DOWN_EN0                  (0x00  <<  \
        SHIFT_FROM_MASK(UP_CLK_CTL1_WB__POWER_DOWN))
        
/*--------------------------------------------------------------------------*/
//      Bit [3..1] XTAL_WU_DURATION, defines time durations in sleep controller clock
//      cycles required by the external resonator (on the XTAL_IN pin) which
//      generates the uP clk to become stable
#ifdef FEATURE_SLEEP_SLOW_CLOCK
#define UP_CLK_CTL1_WB__XTAL_WU_DURATION_52USEC         (2 <<  \
        SHIFT_FROM_MASK(UP_CLK_CTL1_WB__XTAL_WU_DURATION))
#else
#define UP_CLK_CTL1_WB__XTAL_WU_DURATION_52USEC         (6 <<  \
        SHIFT_FROM_MASK(UP_CLK_CTL1_WB__XTAL_WU_DURATION))
#endif

/*--------------------------------------------------------------------------*/
//      Bit [5..4] UP_CLK_SRC_SEL, Selects clock source PIN for the ARM processor
//      Note pin clock frequency may not match associated label
#define UP_CLK_CTL1_WB__UP_CLK_SRC_TCXO                 (0 <<  \
        SHIFT_FROM_MASK(UP_CLK_CTL1_WB__UP_CLK_SRC_SEL))
        
#define UP_CLK_CTL1_WB__UP_CLK_SRC_PLLOUT               (1 <<  \
        SHIFT_FROM_MASK(UP_CLK_CTL1_WB__UP_CLK_SRC_SEL))
        
#define UP_CLK_CTL1_WB__UP_CLK_SRC_SLEEP_XTAL_IN        (3 <<  \
        SHIFT_FROM_MASK(UP_CLK_CTL1_WB__UP_CLK_SRC_SEL))

/*----------------------------------------------------------------------------
  UP Clock Control 2
----------------------------------------------------------------------------*/
#define UP_CLK_CTL2_WB__MCLK_RATE_DIV1                  (0 <<  \
        SHIFT_FROM_MASK(UP_CLK_CTL2_WB__MCLK_RATE))
 
#define UP_CLK_CTL2_WB__MCLK_RATE_DIV2                  (1 <<  \
        SHIFT_FROM_MASK(UP_CLK_CTL2_WB__MCLK_RATE))

#define UP_CLK_CTL2_WB__MCLK_RATE_DIV3                  (2 <<  \
        SHIFT_FROM_MASK(UP_CLK_CTL2_WB__MCLK_RATE))


/*----------------------------------------------------------------------------
  MSM CLK Control 4
----------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
//      Bits [6:0] RESERVED

/*--------------------------------------------------------------------------*/
//      Bit [7] SLEEP_XTAL_EN, this bit specifies if the sleep controller is to be
//      run of the SLEEP_XTAL_IN pin or TCXO/4
#define MSM_CLK_CTL4_WH__SLEEP_XTAL_EN_DIS              (0 <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL4_WH__SLEEP_XTAL_EN))
        
#define MSM_CLK_CTL4_WH__SLEEP_XTAL_EN_ENA              (1 <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL4_WH__SLEEP_XTAL_EN))

/*--------------------------------------------------------------------------*/
//      Bit [8] SLEEP_OSC_RD_BYPASS, set this bit to bypass the resistance in the
//      internal oscillator circuit
#define MSM_CLK_CTL4_WH__SLEEP_OSC_RD_BYPASS_ENA        (1 <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL4_WH__SLEEP_OSC_RD_BYPASS))

#define MSM_CLK_CTL4_WH__SLEEP_OSC_RD_BYPASS_DIS        (0 <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL4_WH__SLEEP_OSC_RD_BYPASS))

/*--------------------------------------------------------------------------*/
//      Bit [9] SLEEP_OSC_RF_BYPASS, set this bit to enable the internal resistance
//      on the schmitt trigger path
#define MSM_CLK_CTL4_WH__SLEEP_OSC_RF_BYPASS_ENA        (1 <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL4_WH__SLEEP_OSC_RF_BYPASS))
        
#define MSM_CLK_CTL4_WH__SLEEP_OSC_RF_BYPASS_DIS        (0 <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL4_WH__SLEEP_OSC_RF_BYPASS))

/*--------------------------------------------------------------------------*/
//      Bit [11:10] SLEEP_OSC_GAIN, configure gain of internal oscillator circuit
#define MSM_CLK_CTL4_WH__SLEEP_OSC_GAIN_000             (0 <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL4_WH__SLEEP_OSC_GAIN))
        
#define MSM_CLK_CTL4_WH__SLEEP_OSC_GAIN_001             (1 <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL4_WH__SLEEP_OSC_GAIN))
        
#define MSM_CLK_CTL4_WH__SLEEP_OSC_GAIN_010             (2 <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL4_WH__SLEEP_OSC_GAIN))
        
#define MSM_CLK_CTL4_WH__SLEEP_OSC_GAIN_011             (3 <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL4_WH__SLEEP_OSC_GAIN))

/*--------------------------------------------------------------------------*/
//      Bit [12] RESERVED

/*--------------------------------------------------------------------------*/
//      Bit [14:13] TCXO_SEL, select the expected input TCXO frequency
#define MSM_CLK_CTL4_WH__TCXO_SEL_1968                  (0 <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL4_WH__TCXO_SEL))
        
#define MSM_CLK_CTL4_WH__TCXO_SEL_1920                  (2 <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL4_WH__TCXO_SEL))
        
#define MSM_CLK_CTL4_WH__TCXO_SEL_1980                  (3 <<  \
        SHIFT_FROM_MASK(MSM_CLK_CTL4_WH__TCXO_SEL))

/*----------------------------------------------------------------------------
  MSM CLK Control 5
----------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
//      Bit [5..4]] VOC_CLK_DIV, defines the division ratio for selected clock
//      source for the QDSP2 Vocoder.

/*      No division */
#define MSM_CLK_CTL5_WH__VOC_CLK_DIV_DIV1         (0 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL5_WH__VOC_CLK_DIV))

/*      Divide by 2 */        
#define MSM_CLK_CTL5_WH__VOC_CLK_DIV_DIV2         (1 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL5_WH__VOC_CLK_DIV))

/*      Divide by 3 */
#define MSM_CLK_CTL5_WH__VOC_CLK_DIV_DIV3         (2 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL5_WH__VOC_CLK_DIV))

/*--------------------------------------------------------------------------*/
//      Bit [7..6]] VOC_CLK_SEL, defines the clock source for the QDSP2 Vocoder.

/*      TCXO */
#define MSM_CLK_CTL5_WH__VOC_CLK_SEL_TCXO         (0 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL5_WH__VOC_CLK_SEL))
        
/*      SLEEP Xtal */
#define MSM_CLK_CTL5_WH__VOC_CLK_SEL_SLEEP_XTAL   (1 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL5_WH__VOC_CLK_SEL))

/*      GPIO28 pin */        
#define MSM_CLK_CTL5_WH__VOC_CLK_SEL_GPIO28       (2 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL5_WH__VOC_CLK_SEL))

/*--------------------------------------------------------------------------*/
//      Bit [8] is RESERVED.

/*--------------------------------------------------------------------------*/
//      Bit [9]] QDSP2_CODEC_EN_N, enables QDSP2 to stop the CODEC core clock.
#define MSM_CLK_CTL5_WH__QDSP2_CODEC_EN_N_ENA       (0 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL5_WH__QDSP2_CODEC_EN_N))
        
#define MSM_CLK_CTL5_WH__QDSP2_CODEC_EN_N_DIS       (1 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL5_WH__QDSP2_CODEC_EN_N))

/*--------------------------------------------------------------------------*/
//      Bit [10] GENERAL_CLK_SEL, defines the clock source for Ringer, Timetick
//      PDM1 and PDM2.
#define MSM_CLK_CTL5_WH__GENERAL_CLK_SEL_TCXO4      (0 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL5_WH__GENERAL_CLK_SEL))
        
#define MSM_CLK_CTL5_WH__GENERAL_CLK_SEL_SLEEP_XTAL (1 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL5_WH__GENERAL_CLK_SEL))

/*--------------------------------------------------------------------------*/
//      Bit [11..14] is RESERVED.

/*--------------------------------------------------------------------------*/
//      Bit [15] SLEEP_4M_32K_SEL, defines the clock source to Sleep controller.
/*      4.096MHz */
#define MSM_CLK_CTL5_WH__SLEEP_4M_32K_SEL_4M        (0 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL5_WH__SLEEP_4M_32K_SEL))

/*      32KHz */        
#define MSM_CLK_CTL5_WH__SLEEP_4M_32K_SEL_32K       (1 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL5_WH__SLEEP_4M_32K_SEL))

/*----------------------------------------------------------------------------
  MSM CLK Control 6
----------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
//      Bit [3..0] TCXODIVSEL, selects the N for the TCXO mod-N counter.
#define MSM_CLK_CTL6_WH__TCXODIVSEL_DIV1          (0x00 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIVSEL))
        
#define MSM_CLK_CTL6_WH__TCXODIVSEL_DIV2          (0x01 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIVSEL))
        
#define MSM_CLK_CTL6_WH__TCXODIVSEL_DIV3          (0x02 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIVSEL))

#define MSM_CLK_CTL6_WH__TCXODIVSEL_DIV4          (0x03 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIVSEL))
        
#define MSM_CLK_CTL6_WH__TCXODIVSEL_DIV5          (0x04 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIVSEL))
        
#define MSM_CLK_CTL6_WH__TCXODIVSEL_DIV6          (0x05 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIVSEL))
        
#define MSM_CLK_CTL6_WH__TCXODIVSEL_DIV7          (0x06 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIVSEL))

#define MSM_CLK_CTL6_WH__TCXODIVSEL_DIV8          (0x07 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIVSEL))

#define MSM_CLK_CTL6_WH__TCXODIVSEL_DIV9          (0x08 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIVSEL))
        
#define MSM_CLK_CTL6_WH__TCXODIVSEL_DIV10         (0x09 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIVSEL))
        
#define MSM_CLK_CTL6_WH__TCXODIVSEL_DIV11         (0x0a << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIVSEL))
        
#define MSM_CLK_CTL6_WH__TCXODIVSEL_DIV12         (0x0b << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIVSEL))
        
#define MSM_CLK_CTL6_WH__TCXODIVSEL_DIV13         (0x0c << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIVSEL))
        
#define MSM_CLK_CTL6_WH__TCXODIVSEL_DIV14         (0x0d << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIVSEL))
        
#define MSM_CLK_CTL6_WH__TCXODIVSEL_DIV15         (0x0e << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIVSEL))
        
#define MSM_CLK_CTL6_WH__TCXODIVSEL_DIV16         (0x0f << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIVSEL))

/*--------------------------------------------------------------------------*/
//      Bit [4] Reserved
 
/*--------------------------------------------------------------------------*/
//      Bit [5] PLLOUTSEL, set this bit to bypass the PLL.
#define MSM_CLK_CTL6_WH__PLLOUTSEL_PLLIN          (0 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__PLLOUTSEL))
        
#define MSM_CLK_CTL6_WH__PLLOUTSEL_PLLOUT         (1 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__PLLOUTSEL))

/*--------------------------------------------------------------------------*/
//      Bit [11..6] Reserved

/*--------------------------------------------------------------------------*/
//      Bit [12] TCXODIV, enables TCXO divide by N counter.
#define MSM_CLK_CTL6_WH__TCXODIV_EN_DIS           (0 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIV_EN))
        
#define MSM_CLK_CTL6_WH__TCXODIV_EN_ENA           (1 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__TCXODIV_EN))

/*--------------------------------------------------------------------------*/
//      Bit [14..13] Reserved

/*--------------------------------------------------------------------------*/
//      Bit [15] CHIPX8_TEST_SEL Set this bit to choose test pin gpio_int50
//      as chipx8 clock; reset this bit to use the normal chipx8 clock coming
//      from chipx16.
#define MSM_CLK_CTL6_WH__CHIPX8_INTERNAL          (0 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__CHIPX8_TEST_SEL))
        
#define MSM_CLK_CTL6_WH__CHIPX8_EXTERNAL          (1 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL6_WH__CHIPX8_TEST_SEL))

/*----------------------------------------------------------------------------
  MSM CLK Control 7
----------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
//      Bit [1:0] DEC_CLK_SEL, defines the clock source for DEC.
#define MSM_CLK_CTL7_WH__DEC_CLK_SEL_CHIPX8             (0x00 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__DEC_CLK_SEL))

#define MSM_CLK_CTL7_WH__DEC_CLK_SEL_TCXO               (0x01 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__DEC_CLK_SEL))

#define MSM_CLK_CTL7_WH__DEC_CLK_SEL_CHIPX16            (0x02 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__DEC_CLK_SEL))
        
#define MSM_CLK_CTL7_WH__DEC_CLK_SEL_PLLOUT_REST_DIV3   (0x03 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__DEC_CLK_SEL))

/*--------------------------------------------------------------------------*/
//      Bit [3:2] SBI_CLK_SEL, defines the clock source for SBI.
#define MSM_CLK_CTL7_WH__SBI_CLK_SEL_TCXO              (0 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__SBI_CLK_SEL))
        
#define MSM_CLK_CTL7_WH__SBI_CLK_SEL_SLEEP_XTAL     (1 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__SBI_CLK_SEL))
        
#define MSM_CLK_CTL7_WH__SBI_CLK_SEL_PLLOUT        (2 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__SBI_CLK_SEL))
        
#define MSM_CLK_CTL7_WH__SBI_CLK_SEL_TCXO4        (3 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__SBI_CLK_SEL))

/*--------------------------------------------------------------------------*/
//      Bit [7:4] CODEC_CLK_SEL, defines the clock source for CODEC.
#define MSM_CLK_CTL7_WH__CODEC_CLK_SEL_PLLOUT_DIV60      (0 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__CODEC_CLK_SEL))
        
#define MSM_CLK_CTL7_WH__CODEC_CLK_SEL_PLLOUT_DIV120     (1 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__CODEC_CLK_SEL))
        
#define MSM_CLK_CTL7_WH__CODEC_CLK_SEL_PLLOUT_DIV240     (2 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__CODEC_CLK_SEL))
        
#define MSM_CLK_CTL7_WH__CODEC_CLK_SEL_PLLOUT_DIV24      (3 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__CODEC_CLK_SEL))
#define MSM_CLK_CTL7_WH__CODEC_CLK_SEL_PLLOUT_DIV48      (4 << \
        SHIFT_FROM_MASK(MSM_CLK_CTL7_WH__CODEC_CLK_SEL))