msm6000bits.h
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#ifndef MSM6000BITS_H
#define MSM6000BITS_H
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// _ --
// _/ \_ --
// CDMA DIGITAL CELLULAR / \_/ \ --
// \_/ \_/ --
// / \_/ \ --
// MOBILE STATION MODEM - MSM6000 \_/ \_/ --
// \_/ --
// --
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//
// This file define bits for all the registers in MSM510X.
//
//-----------------------------------------------------------------------------
// QUALCOMM PROPRIETARY
// Copyright (c) 2002 by Qualcomm Incorporated
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// EDIT HISTORY FOR FILE
//
// $Header: L:/src/asw/MSM6000/vcs/msm6000bits.h_v 1.8 21 Jul 2004 14:53:16 cromero $
//
// This section contains comments describing changes made to the module.
// Notice that changes are listed in reverse chronological order.
//
//
// when who what, where, why
// -------- --- ---------------------------------------------------------
// 10/09/02 bgc Corrected incorrect bit shifts on MSM_CLK_CTL8 bits.
// 01/08/02 bgc Moved SBI_CTL definitions in from sbii.h
// 09/18/01 hjr Created from msm510xbits.h
//-----------------------------------------------------------------------------
//#include "target.h"
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//
// MACROS DEFINITIONS
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
/*-----------------------------------------------------------------------------
SHIFT_TEST
This macro returns a 1 (TRUE) if the specified bit in the mask is equal to 1,
else it returns a 0.
INPUT:
val = MASK
shift = Specified bit
NOTE: See SHIFT_FROM_MASK
-----------------------------------------------------------------------------*/
#define SHIFT_TEST( val , shift ) ( (val) & (0x01<<(shift)))
/*-----------------------------------------------------------------------------
SHIFT_GET
This macro is used by SHIFT_FROM_MASK to test if the specified bit in the mask
is equal 1 or 0. If the specified bit equal to 1 then it returns # of shifts else
check the next bit.
INPUT:
val = MASK
shift = Current bit
next_shift = Next bit
NOTE: See SHIFT_FROM_MASK
-----------------------------------------------------------------------------*/
#define SHIFT_GET( val, shift, next_shift) (SHIFT_TEST((val),(shift)) ? \
(shift) : (next_shift))
/*-----------------------------------------------------------------------------
SHIFT_FROM_MASK
This macro uses the register mask definitions in msmXXXXreg.h to calculate
how many times a bit value needs to be shifted so that it modifies the correct
bit within a register.
MACRO FORMAT:
if ((MASK && 0x01) != 0)
return 0; //if 1st bit = 1 then do not shift
else
if ((MASK && 0x02) != 0)
return 1; //if 2nd bit = 1 then shift once
else
if ((MASK && 0x04) != 0)
return 2; //if 3rd bit = 1 then shift twice
else
if ((MASK && 0x08) != 0)
return 3; //if 4th bit = 1 then shift three
else
...... //we check until bit 31
......
......
INPUT:
x = MASK
NOTE: ONLY A MASK DEFINITION CAN BE USE AS AN INPUT FOR THIS MACRO!.
THIS MACRO PRODUCES NO CODE, IT RETURNS A CONSTANT!.
----------------------------------------------------------------------------*/
#define SHIFT_FROM_MASK(x) (SHIFT_TEST(x##_MASK,0) ? 0 : \
(SHIFT_GET(x##_MASK,1, \
(SHIFT_GET(x##_MASK,2, \
(SHIFT_GET(x##_MASK,3, \
(SHIFT_GET(x##_MASK,4, \
(SHIFT_GET(x##_MASK,5, \
(SHIFT_GET(x##_MASK,6, \
(SHIFT_GET(x##_MASK,7, \
(SHIFT_GET(x##_MASK,8, \
(SHIFT_GET(x##_MASK,9, \
(SHIFT_GET(x##_MASK,10, \
(SHIFT_GET(x##_MASK,11, \
(SHIFT_GET(x##_MASK,12, \
(SHIFT_GET(x##_MASK,13, \
(SHIFT_GET(x##_MASK,14, \
(SHIFT_GET(x##_MASK,15, \
(SHIFT_GET(x##_MASK,16, \
(SHIFT_GET(x##_MASK,17, \
(SHIFT_GET(x##_MASK,18, \
(SHIFT_GET(x##_MASK,19, \
(SHIFT_GET(x##_MASK,20, \
(SHIFT_GET(x##_MASK,21, \
(SHIFT_GET(x##_MASK,22, \
(SHIFT_GET(x##_MASK,23, \
(SHIFT_GET(x##_MASK,24, \
(SHIFT_GET(x##_MASK,25, \
(SHIFT_GET(x##_MASK,26, \
(SHIFT_GET(x##_MASK,27, \
(SHIFT_GET(x##_MASK,28, \
(SHIFT_GET(x##_MASK,29, \
(SHIFT_GET(x##_MASK,30, \
(SHIFT_GET(x##_MASK,31,0) \
) )))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))
/*----------------------------------------------------------------------------
SHIFT_DN_FROM_MASK
This macro uses the register mask definitions in msmXXXXreg.h to calculate
how many times a bit value needs to be shifted so that it modifies the correct
bit within a register.
The design is identical to SHIFT_FROM_MASK except that the full name of the
mask is used. This is needed for use in existing that already take the full
mask name as a parameter.
INPUT:
x = MASK
NOTE: ONLY A MASK DEFINITION CAN BE USE AS AN INPUT FOR THIS MACRO!.
THIS MACRO PRODUCES NO CODE, IT RETURNS A CONSTANT!.
---------------------------------------------------------------------------*/
#define SHIFT_DN_FROM_MASK(x) \
((x & 0x00000001) ? 0 : \
((x & 0x00000002) ? 1 : \
((x & 0x00000004) ? 2 : \
((x & 0x00000008) ? 3 : \
((x & 0x00000010) ? 4 : \
((x & 0x00000020) ? 5 : \
((x & 0x00000040) ? 6 : \
((x & 0x00000080) ? 7 : \
((x & 0x00000100) ? 8 : \
((x & 0x00000200) ? 9 : \
((x & 0x00000400) ? 10 : \
((x & 0x00000800) ? 11 : \
((x & 0x00001000) ? 12 : \
((x & 0x00002000) ? 13 : \
((x & 0x00004000) ? 14 : \
((x & 0x00008000) ? 15 : \
((x & 0x00010000) ? 16 : \
((x & 0x00020000) ? 17 : \
((x & 0x00040000) ? 18 : \
((x & 0x00080000) ? 19 : \
((x & 0x00100000) ? 20 : \
((x & 0x00200000) ? 21 : \
((x & 0x00400000) ? 22 : \
((x & 0x00800000) ? 23 : \
((x & 0x01000000) ? 24 : \
((x & 0x02000000) ? 25 : \
((x & 0x04000000) ? 26 : \
((x & 0x08000000) ? 27 : \
((x & 0x10000000) ? 28 : \
((x & 0x20000000) ? 29 : \
((x & 0x40000000) ? 30 : \
((x & 0x80000000) ? 31 : 0 \
))))))))))))))))))))))))))))))))
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//
// BOOT CODE BITS DEFINITIONS
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
/*----------------------------------------------------------------------------
GPIO FUNCTION Select
----------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
// Bit [4] PCS6_CS_SEL, when set (1), the RAM2_CS_N function is selected
// for the GPIO_INT37 pin
#define GPIO_INT_FUNC_SEL_0_PCS6_CS_ENA (0x01 << \
SHIFT_FROM_MASK(GPIO_INT_FUNCTION_SEL_0_WH__PCS6_CS_SEL))
#define GPIO_INT_FUNC_SEL_0_PCS6_CS_DIS (0x00 << \
SHIFT_FROM_MASK(GPIO_INT_FUNCTION_SEL_0_WH__PCS6_CS_SEL))
/*--------------------------------------------------------------------------*/
// Bit [11:12] These bits are used to mux out TX IQ data or TX IQ DAC
// inputs through GPIOs for testing purpose.
#define GPIO_INT_FUNC_SEL_0_WH__TX_DATA_SEL__GPIO_INT (0x00 << \
SHIFT_FROM_MASK(GPIO_INT_FUNCTION_SEL_0_WH__TX_DATA_SEL))
#define GPIO_INT_FUNC_SEL_0_WH__TX_DATA_SEL__TX_IQDATA (0x01 << \
SHIFT_FROM_MASK(GPIO_INT_FUNCTION_SEL_0_WH__TX_DATA_SEL))
#define GPIO_INT_FUNC_SEL_0_WH__TX_DATA_SEL__TX_IDAC (0x02 << \
SHIFT_FROM_MASK(GPIO_INT_FUNCTION_SEL_0_WH__TX_DATA_SEL))
#define GPIO_INT_FUNC_SEL_0_WH__TX_DATA_SEL__TX_QDAC (0x03 << \
SHIFT_FROM_MASK(GPIO_INT_FUNCTION_SEL_0_WH__TX_DATA_SEL))
/*--------------------------------------------------------------------------*/
// Bit [13] GPIO_INT12_SEL (LB_N_SEL), When set, Outputs lb_n_signal on
// GPIO_INT12
#define GPIO_INT_FUNC_SEL_1_LB_N_ENA (0x01 << \
SHIFT_FROM_MASK(GPIO_INT_FUNCTION_SEL_1_WH__GPIO_INT12_SEL))
#define GPIO_INT_FUNC_SEL_1_LB_N_DIS (0x00 << \
SHIFT_FROM_MASK(GPIO_INT_FUNCTION_SEL_1_WH__GPIO_INT12_SEL))
/*----------------------------------------------------------------------------
GPIO Interrupt/Address Select
----------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
// Bit [1] ADDR_21_EN, when set address bit 21 is selected as the source
// for GPIO_INT3
#define GPIO_INT_ADDR_SEL_WH__ADDRESS_21_ENA (0x01 << \
SHIFT_FROM_MASK(GPIO_INT_ADDR_SEL_WH__ADDRESS_21_EN))
#define GPIO_INT_ADDR_SEL_WH__ADDRESS_21_DIS (0x00 << \
SHIFT_FROM_MASK(GPIO_INT_ADDR_SEL_WH__ADDRESS_21_EN))
/*--------------------------------------------------------------------------*/
// Bit [2] ADDR_22_EN, when set address bit 22 is selected as the source
// for GPIO_INT2
#define GPIO_INT_ADDR_SEL_WH__ADDRESS_22_ENA (0x01 << \
SHIFT_FROM_MASK(GPIO_INT_ADDR_SEL_WH__ADDRESS_22_EN))
#define GPIO_INT_ADDR_SEL_WH__ADDRESS_22_DIS (0x00 << \
SHIFT_FROM_MASK(GPIO_INT_ADDR_SEL_WH__ADDRESS_22_EN))
/*----------------------------------------------------------------------------
MSM Wait
----------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
// Bit [3..0] MSM_WAIT sets minimum number of wait states for a MSM register
// access
#define MSM_WAIT_WH_0WAIT (0x00 << \
SHIFT_FROM_MASK(MSM_WAIT_WH__MSM_WAIT))
#define MSM_WAIT_WH_1WAIT (0x01 << \
SHIFT_FROM_MASK(MSM_WAIT_WH__MSM_WAIT))
/*----------------------------------------------------------------------------
SWITCH_CLK
----------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
// Bit [0] SWITCH, switch to the clock source selected.
//
#define SWITCH_CLK_WB__UP_CLK_CTL1 (0 << \
SHIFT_FROM_MASK(SWITCH_CLK_WB))
#define SWITCH_CLK_WB__UP_CLK_CTL0 (1 << \
SHIFT_FROM_MASK(SWITCH_CLK_WB))
/*----------------------------------------------------------------------------
UP Clock Control 0
----------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
// Bit [2:0] UP_CLK_SRC_SEL1, Selects clock source PIN for the ARM processor
// Note pin clock frequency may not match associated label
#define UP_CLK_CTL0_WB__UP_CLK_SRC_TCXO (0 << \
SHIFT_FROM_MASK(UP_CLK_CTL0_RB__UP_CLK_SRC_SEL1))
#define UP_CLK_CTL0_WB__UP_CLK_SRC_PLLOUT (1 << \
SHIFT_FROM_MASK(UP_CLK_CTL0_RB__UP_CLK_SRC_SEL1))
#define UP_CLK_CTL0_WB__UP_CLK_SRC_SLEEP_XTAL_IN (3 << \
SHIFT_FROM_MASK(UP_CLK_CTL0_RB__UP_CLK_SRC_SEL1))
/*--------------------------------------------------------------------------*/
// Bit [3] CLKSRC_SWITCH_EN, Enables on the fly clock source switching
//
#define UP_CLK_CTL0_WB__CLKSRC_SWITCH_EN_ON (1 << \
SHIFT_FROM_MASK(UP_CLK_CTL0_WB__CLKSRC_SWITCH_EN))
#define UP_CLK_CTL0_WB__CLKSRC_SWITCH_EN_OFF (0 << \
SHIFT_FROM_MASK(UP_CLK_CTL0_WB__CLKSRC_SWITCH_EN))
/*----------------------------------------------------------------------------
UP Clock Control 1
----------------------------------------------------------------------------*/
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