msm6000reg.h

在高通的手机平台下,一个下载手机.bin文件到手机的flash中的工具,包含PC端的程序代码和运行在基带处理器中的代码.

#define DFM_DC_PDM_0_WB                               0x03000520
#define DFM_DC_PDM_0_WB_MASK                                0xff
#define DFM_DC_PDM_1_WB                               0x03000524
#define DFM_DC_PDM_1_WB_MASK                                0xff
#define DFM_DC_PDM_2_WB                               0x03000528
#define DFM_DC_PDM_2_WB_MASK                                0x7f
#define DFM_DC_PDM_2_WB__DC_PDM_RANGE_SEL_MASK              0x40
#define DFM_DC_PDM_2_WB__Q_DC_OFFSET_FREEZE_MASK            0x20
#define DFM_DC_PDM_2_WB__I_DC_OFFSET_FREEZE_MASK            0x10
#define DFM_DC_PDM_2_WB__Q_DC_IN_SEL_MASK                    0x8
#define DFM_DC_PDM_2_WB__I_DC_IN_SEL_MASK                    0x4
#define DFM_DC_PDM_2_WB__Q_DC_OFFSET_MSB_MASK                0x2
#define DFM_DC_PDM_2_WB__I_DC_OFFSET_MSB_MASK                0x1
#define DFM_RXAGC_PDM_0_WB                            0x0300052c
#define DFM_RXAGC_PDM_0_WB_MASK                             0xff
#define DFM_RXAGC_PDM_0_WB__RXAGC_IN_SEL_MASK               0x80
#define DFM_RXAGC_PDM_0_WB__RXAGC_PDM_OVERRIDE_MASK         0x7f
#define DFM_FREQ_PDM_0_WB                             0x03000530
#define DFM_FREQ_PDM_0_WB_MASK                              0xff
#define DFM_FREQ_PDM_1_WB                             0x03000534
#define DFM_FREQ_PDM_1_WB_MASK                               0x7
#define DFM_FREQ_PDM_1_WB__FREQ_TRACK_FREEZE_MASK            0x4
#define DFM_FREQ_PDM_1_WB__FREQ_IN_SEL_MASK                  0x2
#define DFM_FREQ_PDM_1_WB__FREQ_IN_MSB_MASK                  0x1
#define DFM_VOC_INTF_CONFIG_WB                        0x03000538
#define DFM_VOC_INTF_CONFIG_WB_MASK                          0x7
#define DFM_VOC_INTF_CONFIG_WB__DFM_LOOPBACK_MASK            0x4
#define DFM_VOC_INTF_CONFIG_WB__VOC_LOOPBACK_MASK            0x2
#define DFM_VOC_INTF_CONFIG_WB__FM_REQ_SEL_MASK              0x1
#define DFM_TXWBD_INTF_0_WB                           0x03000540
#define DFM_TXWBD_INTF_0_WB_MASK                            0xff
#define DFM_TXWBD_INTF_1_WB                           0x03000544
#define DFM_TXWBD_INTF_1_WB_MASK                            0xff
#define DFM_MAX_TX_PWR_0_WB                           0x03000548
#define DFM_MAX_TX_PWR_0_WB_MASK                            0xff
#define DFM_MAX_TX_PWR_1_WB                           0x0300054c
#define DFM_MAX_TX_PWR_1_WB_MASK                             0x7
#define DFM_MAX_TX_PWR_1_WB__TXAGC_PDM_OE_MASK               0x4
#define DFM_MAX_TX_PWR_1_WB__TXAGC_POLARITY_MASK             0x2
#define DFM_MAX_TX_PWR_1_WB__TXAGC_PDM_MSB_MASK              0x1
#define DFM_FREQ_SENS_GAIN_WB                         0x03000550
#define DFM_FREQ_SENS_GAIN_WB_MASK                          0x3f
#define DFM_TXFM_CONFIG_WB                            0x03000554
#define DFM_TXFM_CONFIG_WB_MASK                              0xf
#define DFM_TXFM_CONFIG_WB__DFM_SPECTRAL_INVERSION_MASK         0x8
#define DFM_TXFM_CONFIG_WB__TXAGC_TRI_EN_MASK                0x4
#define DFM_TXFM_CONFIG_WB__DFM_TXCTL_EN_MASK                0x2
#define DFM_TXFM_CONFIG_WB__TX_AUDIO_MUTE_MASK               0x1
#define DFM_MIN1_BYTE_0_WB                            0x03000558
#define DFM_MIN1_BYTE_0_WB_MASK                             0xff
#define DFM_MIN1_BYTE_1_WB                            0x0300055c
#define DFM_MIN1_BYTE_1_WB_MASK                             0xff
#define DFM_MIN1_BYTE_2_WB                            0x03000560
#define DFM_MIN1_BYTE_2_WB_MASK                             0xff
#define DFM_RXWBD_BANDWIDTH_WB                        0x03000564
#define DFM_RXWBD_BANDWIDTH_WB_MASK                         0x7f
#define DFM_RXWBD_BANDWIDTH_WB__DPLL_FALSELOCK_EN_MASK        0x40
#define DFM_RXWBD_BANDWIDTH_WB__WBD_ACQ_BW_MASK             0x38
#define DFM_RXWBD_BANDWIDTH_WB__WBD_TRK_BW_MASK              0x7
#define DFM_RXWBD_CONFIG_0_WB                         0x03000568
#define DFM_RXWBD_CONFIG_0_WB_MASK                          0xff
#define DFM_RXWBD_CONFIG_0_WB__BCH_BYPASS_MASK              0x80
#define DFM_RXWBD_CONFIG_0_WB__ANY_DATA_INT_EN_MASK         0x40
#define DFM_RXWBD_CONFIG_0_WB__MY_DATA_INT_EN_MASK          0x20
#define DFM_RXWBD_CONFIG_0_WB__WS_SEL_MASK                  0x10
#define DFM_RXWBD_CONFIG_0_WB__FVC_MVOTE_MODE_MASK           0x8
#define DFM_RXWBD_CONFIG_0_WB__ROAM_STAT_MASK                0x4
#define DFM_RXWBD_CONFIG_0_WB__WBD_RX_INV_MASK               0x2
#define DFM_RXWBD_CONFIG_0_WB__FOCC_FVC_SEL_MASK             0x1
#define DFM_RXWBD_WR_WB                               0x0300056c
#define DFM_RXWBD_WR_WB_MASK                                 0x3
#define DFM_RXWBD_WR_WB__NRZDATA_WR_MASK                     0x2
#define DFM_RXWBD_WR_WB__NRZDATA_WR_MODE_MASK                0x1
#define DFM_RXAGC_PDM_1_WB                            0x03000570
#define DFM_RXAGC_PDM_1_WB_MASK                              0x1
#define DFM_RXAGC_PDM_1_WB__RXAGC_PDM_FREEZE_MASK            0x1
#define DFM_RXWBD_CONFIG_1_WB                         0x03000574
#define DFM_RXWBD_CONFIG_1_WB_MASK                           0x3
#define DFM_RXWBD_CONFIG_1_WB__AUDIO_LOW_PWR_EN_MASK         0x2
#define DFM_RXWBD_CONFIG_1_WB__FOCC_MVOTE_MODE_MASK          0x1
#define DFM_SLOT_CTL_1_WB                             0x03000578
#define DFM_SLOT_CTL_1_WB_MASK                               0x1
#define DFM_SLOT_CTL_1_WB__RF_SLEEP_MVOTE_MODE_MASK          0x1
#define DFM_SLOT_PDM_CTL_WB                           0x0300057c
#define DFM_SLOT_PDM_CTL_WB_MASK                             0xf
#define DFM_SLOT_PDM_CTL_WB__IQ_OFFSET_TRI_EN_MASK           0x8
#define DFM_SLOT_PDM_CTL_WB__RXAGC_TRI_EN_MASK               0x4
#define DFM_SLOT_PDM_CTL_WB__FREQ_TRACK_TRI_EN_MASK          0x2
#define DFM_SLOT_PDM_CTL_WB__PDM_LOW_PWR_EN_MASK             0x1
#define DFM_SLOT_CTL_WB                               0x03000580
#define DFM_SLOT_CTL_WB_MASK                                0xff
#define DFM_SLOT_CTL_WB__SLEEP_FORCE_N_MASK                 0x80
#define DFM_SLOT_CTL_WB__SLEEP_OVERRIDE_N_MASK              0x40
#define DFM_SLOT_CTL_WB__STREAM_SLOT_EN_MASK                0x20
#define DFM_SLOT_CTL_WB__SYNC_ERASE_EN_MASK                 0x10
#define DFM_SLOT_CTL_WB__FILLER_EN_MASK                      0x8
#define DFM_SLOT_CTL_WB__CRC_EN_MASK                         0x4
#define DFM_SLOT_CTL_WB__MAJORITY_EN_MASK                    0x2
#define DFM_SLOT_CTL_WB__SLEEP_EN_MASK                       0x1
#define DFM_DPLL_WU_TIMER_WB                          0x03000584
#define DFM_DPLL_WU_TIMER_WB_MASK                           0xff
#define DFM_SYNC_WU_TIMER_WB                          0x03000588
#define DFM_SYNC_WU_TIMER_WB_MASK                           0xff
#define DFM_DATA_WU_TIMER_WB                          0x0300058c
#define DFM_DATA_WU_TIMER_WB_MASK                           0xff
#define DFM_STREAM_SLOT_TIMER_WB                      0x03000590
#define DFM_STREAM_SLOT_TIMER_WB_MASK                       0x3f
#define DFM_RF_WU_OFFSET_WB                           0x03000594
#define DFM_RF_WU_OFFSET_WB_MASK                            0x7f
#define DFM_NCO_TEST0_WB                              0x03000598
#define DFM_NCO_TEST0_WB_MASK                               0xff
#define DFM_NCO_TEST0_WB__NCO_TEST_DATA_7_0_MASK            0xff
#define DFM_NCO_TEST1_WB                              0x0300059c
#define DFM_NCO_TEST1_WB_MASK                               0xff
#define DFM_NCO_TEST1_WB__NCO_RESET_MASK                    0x80
#define DFM_NCO_TEST1_WB__NCO_TEST_MASK                     0x40
#define DFM_NCO_TEST1_WB__BYPASS_NCO_MASK                   0x20
#define DFM_NCO_TEST1_WB__NCO_DC_CORR_EN_MASK               0x10
#define DFM_NCO_TEST1_WB__NCO_TEST_DATA_11_8_MASK            0xf
#define DFM_LOOPBACK_CNTL_WB                          0x030005ac
#define DFM_LOOPBACK_CNTL_WB_MASK                            0x1
#define DFM_LOOPBACK_CNTL_WB__RX_LOOPBACK_EN_MASK            0x1
#define DFM_LNA_CNTL_0_WB                             0x030005b0
#define DFM_LNA_CNTL_0_WB_MASK                               0xf
#define DFM_LNA_CNTL_0_WB__DFM_AGC_DC_GAIN_EN_MASK           0x8
#define DFM_LNA_CNTL_0_WB__DFM_AGC_SBI_BYPASS_MASK           0x4
#define DFM_LNA_CNTL_0_WB__DFM_AGC_SBI_EN_MASK               0x2
#define DFM_LNA_CNTL_0_WB__DFM_LNA_STEP_GAIN_EN_MASK         0x1
#define DFM_LNA_OFFSET_WH                             0x030005b4
#define DFM_LNA_OFFSET_WH_MASK                             0x3ff
#define DFM_LNA_FALL_WB                               0x030005b8
#define DFM_LNA_FALL_WB_MASK                                0xff
#define DFM_LNA_RISE_WB                               0x030005bc
#define DFM_LNA_RISE_WB_MASK                                0xff
#define DFM_LNA_BYPASS_TIMER_WH                       0x030005c0
#define DFM_LNA_BYPASS_TIMER_WH_MASK                      0xffff
#define DFM_LNA_NONBYPASS_TIMER_WH                    0x030005c4
#define DFM_LNA_NONBYPASS_TIMER_WH_MASK                   0xffff
#define DFM_LNA_FOLLOWER_DELAY_WB                     0x030005c8
#define DFM_LNA_FOLLOWER_DELAY_WB_MASK                       0x3
#define DFM_LNA_RANGE_DELAY_WH                        0x030005cc
#define DFM_LNA_RANGE_DELAY_WH_MASK                        0x1ff
#define DFM_AGC_ACC_MIN_1_WB                          0x030005d0
#define DFM_AGC_ACC_MIN_1_WB_MASK                           0x3f
#define DFM_AGC_IM_GAIN_WB                            0x030005d4
#define DFM_AGC_IM_GAIN_WB_MASK                             0xff
#define DFM_AGC_DC_GAIN_WB                            0x030005d8
#define DFM_AGC_DC_GAIN_WB_MASK                             0xff
#define DFM_LNA_CNTL_1_WB                             0x030005dc
#define DFM_LNA_CNTL_1_WB_MASK                               0x7
#define DFM_LNA_CNTL_1_WB__DFM_LNA_RANGE_FORCE_CTL_MASK         0x4
#define DFM_LNA_CNTL_1_WB__DFM_LNA_DATA_CTL_N_MASK           0x2
#define DFM_LNA_CNTL_1_WB__DFM_LNA_POLARITY_MASK             0x1
#define DFM_LNA_ORIDE_DATA_WB                         0x030005e0
#define DFM_LNA_ORIDE_DATA_WB_MASK                           0x3
#define DFM_LNA_ORIDE_DATA_WB__DFM_LNA_RANGE_FORCE_MASK         0x2
#define DFM_LNA_ORIDE_DATA_WB__DFM_LNA_RANGE_DATA_MASK         0x1
#define DFM_DATA_FREEZE_CTL_WB                        0x030005ec
#define DFM_DATA_FREEZE_CTL_WB_MASK                          0x1
#define DFM_DATA_FREEZE_CTL_WB__DATA_FREEZE_EN_MASK          0x1
#define DFM_DATA_FREEZE_DELAY_WH                      0x030005f0
#define DFM_DATA_FREEZE_DELAY_WH_MASK                      0x1ff
#define DFM_DATA_FREEZE_DELAY_WH__DATA_FREEZE_DELAY_VAL_MASK       0x1ff
#define CALIBRATION_CTL_WB                            0x030005f4
#define CALIBRATION_CTL_WB_MASK                              0x3
#define CALIBRATION_CTL_WB__CALIBRATION_EN_CDMA_DFM_MASK         0x3
#define DFM_LNA_DECISION_DELAY_WB                     0x030005f8
#define DFM_LNA_DECISION_DELAY_WB_MASK                      0xff
#define DFM_IM_LEVEL1_WB                              0x030005fc
#define DFM_IM_LEVEL1_WB_MASK                               0xff
//-----------------------------------------------------------------------------
// MSM MEMORY SPACE (CHIP_BASE + 0x500) to (CHIP_BASE + 0x59C)
//
//  SECTION     DFM READ REGISTERS
//-----------------------------------------------------------------------------
#define DFM_RXIQ_STATUS_0_RB                          0x03000508
#define DFM_RXIQ_STATUS_0_RB_MASK                           0xff
#define DFM_RX_AGC_FILTER_RB                          0x0300050c
#define DFM_RX_AGC_FILTER_RB_MASK                           0xff
#define DFM_RX_AGC_RSSI_RB                            0x03000510
#define DFM_RX_AGC_RSSI_RB_MASK                             0x7f
#define DFM_TXWBD_STATUS_RB                           0x03000548
#define DFM_TXWBD_STATUS_RB_MASK                             0x7
#define DFM_TXWBD_STATUS_RB__TXFM_WBD_MUTE_MASK              0x4
#define DFM_TXWBD_STATUS_RB__DFM_TXCTL_MASK                  0x2
#define DFM_TXWBD_STATUS_RB__IDLE_BUSY_N_MASK                0x1
#define DFM_RXWBD_STAT_4_RB                           0x03000550
#define DFM_RXWBD_STAT_4_RB_MASK                             0xf
#define DFM_RXWBD_STAT_4_RB__BCH_PARITY_11_8_MASK            0xf
#define DFM_RXWBD_STAT_5_RB                           0x03000554
#define DFM_RXWBD_STAT_5_RB_MASK                            0xff
#define DFM_RXWBD_STAT_5_RB__BCH_PARITY_7_0_MASK            0xff
#define DFM_RXWBD_STAT_0_RB                           0x03000558
#define DFM_RXWBD_STAT_0_RB_MASK                            0xff
#define DFM_RXWBD_STAT_0_RB__BCH_DATA_7_0_MASK              0xff
#define DFM_RXWBD_STAT_1_RB                           0x0300055c
#define DFM_RXWBD_STAT_1_RB_MASK                            0xff
#define DFM_RXWBD_STAT_1_RB__BCH_DATA_15_8_MASK             0xff
#define DFM_RXWBD_STAT_2_RB                           0x03000560
#define DFM_RXWBD_STAT_2_RB_MASK                            0xff
#define DFM_RXWBD_STAT_2_RB__BCH_DATA_23_16_MASK            0xff
#define DFM_RXWBD_STAT_3_RB                           0x03000564
#define DFM_RXWBD_STAT_3_RB_MASK                            0xff
#define DFM_RXWBD_STAT_3_RB__BCH_STATUS_MASK                0xc0
#define DFM_RXWBD_STAT_3_RB__BCH_DATA_27_24_MASK             0xf
#define DFM_WORD_SYNC_COUNT_RB                        0x03000568
#define DFM_WORD_SYNC_COUNT_RB_MASK                         0xff
#define DFM_RXWBD_RD_RB                               0x03