📄 msm6000reg.h
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#define MOD_STATUS_RB__SCH_ENC_ERROR_MASK 0x4
#define MOD_STATUS_RB__FCH_ENCODING_MASK 0x2
#define MOD_STATUS_RB__FCH_ENC_ERROR_MASK 0x1
//-----------------------------------------------------------------------------
// MSM MEMORY SPACE (CHIP_BASE + 0x2E0) to (CHIP_BASE + 0x39C)
//
// SECTION DECODER (SVD) WRITE REGISTERS
//-----------------------------------------------------------------------------
#define VD_RESET_WB 0x030002e0
#define VD_RESET_WB_MASK 0xff
#define VD_MODE_WB 0x03000300
#define VD_MODE_WB_MASK 0xf
#define VD_MODE_WB__INITMODE_MASK 0xe
#define VD_MODE_WB__PACKET_MASK 0x1
#define VDPOLY2IJ_WH 0x03000304
#define VDPOLY2IJ_WH_MASK 0x3fff
#define VDPOLY3IJ_WH 0x03000308
#define VDPOLY3IJ_WH_MASK 0x3fff
#define VDPOLY3K_WB 0x0300030c
#define VDPOLY3K_WB_MASK 0x7f
#define VDPOLY4IJ_WH 0x03000310
#define VDPOLY4IJ_WH_MASK 0x3fff
#define VDPOLY4KL_WH 0x03000314
#define VDPOLY4KL_WH_MASK 0x3fff
#define VD_TESTCON_WB 0x0300033c
#define VD_TESTCON_WB_MASK 0x3
// RDMUX BIT[1:0]
//-----------------------------------------------------------------------------
// MSM MEMORY SPACE (CHIP_BASE + 0x2E0) to (CHIP_BASE + 0x39C)
//
// SECTION DECODER (SVD) READ REGISTERS
//-----------------------------------------------------------------------------
#define VD_TESTOUT_RH 0x03000330
#define VD_TESTOUT_RH_MASK 0xffff
//-----------------------------------------------------------------------------
// MSM MEMORY SPACE (CHIP_BASE + 0x3A0) to (CHIP_BASE + 0x3FC)
//
// SECTION UART2 WRITE REGISTERS
//-----------------------------------------------------------------------------
#define UART2_MR1_WB 0x030003ac
#define UART2_MR1_WB_MASK 0xff
#define UART2_MR1_WB__RX_RDY_CTL_MASK 0x80
#define UART2_MR1_WB__CTS_CTL_MASK 0x40
#define UART2_MR1_WB__AUTO_RFR_LEVEL_MASK 0x3f
#define UART2_MR2_WB 0x030003b0
#define UART2_MR2_WB_MASK 0xff
#define UART2_MR2_WB__LOOPBACK_MASK 0x80
#define UART2_MR2_WB__ERROR_MODE_MASK 0x40
#define UART2_MR2_WB__BITS_PER_CHAR_MASK 0x30
#define UART2_MR2_WB__STOP_BIT_LEN_MASK 0xc
#define UART2_MR2_WB__PARITY_MODE_MASK 0x3
#define UART2_CSR_WB 0x030003b4
#define UART2_CSR_WB_MASK 0xff
#define UART2_CSR_WB__UART_RX_CLK_SEL_MASK 0xf0
#define UART2_CSR_WB__UART_TX_CLK_SEL_MASK 0xf
#define UART2_TF_WB 0x030003b8
#define UART2_TF_WB_MASK 0xff
#define UART2_CR_WB 0x030003bc
#define UART2_CR_WB_MASK 0xff
#define UART2_CR_WB__CHANNEL_COMMAND_MASK 0xf0
#define UART2_CR_WB__UART_TX_DISABLE_MASK 0x8
#define UART2_CR_WB__UART_TX_EN_MASK 0x4
#define UART2_CR_WB__UART_RX_DISABLE_MASK 0x2
#define UART2_CR_WB__UART_RX_EN_MASK 0x1
#define UART2_IMR_WB 0x030003c0
#define UART2_IMR_WB_MASK 0x7f
#define UART2_IMR_WB__CURRENT_CTS_MASK 0x40
#define UART2_IMR_WB__DELTA_CTS_MASK 0x20
#define UART2_IMR_WB__RXLEV_MASK 0x10
#define UART2_IMR_WB__RXSTALE_MASK 0x8
#define UART2_IMR_WB__RXBREAK_MASK 0x4
#define UART2_IMR_WB__RXHUNT_MASK 0x2
#define UART2_IMR_WB__TXLEV_MASK 0x1
#define UART2_IPR_WB 0x030003c4
#define UART2_IPR_WB_MASK 0xff
#define UART2_IPR_WB__STALE_TIMEOUT_MSB_MASK 0x80
#define UART2_IPR_WB__SAMPLE_DATA_MASK 0x40
#define UART2_IPR_WB__RXSTALE_LAST_MASK 0x20
#define UART2_IPR_WB__STALE_TIMEOUT_LSB_MASK 0x1f
#define UART2_TFWR_WB 0x030003c8
#define UART2_TFWR_WB_MASK 0x3f
#define UART2_TFWR_WB__TFW_MASK 0x3f
#define UART2_RFWR_WB 0x030003cc
#define UART2_RFWR_WB_MASK 0x3f
#define UART2_RFWR_WB__RFW_MASK 0x3f
#define UART2_HCR_WB 0x030003d0
#define UART2_HCR_WB_MASK 0xff
#define UART2_MREG_WB 0x030003d4
#define UART2_MREG_WB_MASK 0xff
#define UART2_NREG_WB 0x030003d8
#define UART2_NREG_WB_MASK 0xff
#define UART2_DREG_WB 0x030003dc
#define UART2_DREG_WB_MASK 0xff
#define UART2_MNDREG_WB 0x030003e0
#define UART2_MNDREG_WB_MASK 0x3f
#define UART2_MNDREG_WB__MREG_LSB_MASK 0x20
#define UART2_MNDREG_WB__NREG_LSB_MASK 0x1c
#define UART2_MNDREG_WB__DREG_LSB_MASK 0x3
#define UART2_IRDA_WB 0x030003e4
#define UART2_IRDA_WB_MASK 0xf
#define UART2_IRDA_WB__IRDA_LOOPBACK_MASK 0x8
#define UART2_IRDA_WB__INVERT_IRDA_TX_MASK 0x4
#define UART2_IRDA_WB__INVERT_IRDA_RX_MASK 0x2
#define UART2_IRDA_WB__IRDA_EN_MASK 0x1
#define UART2_SIM_CFG_WH 0x030003e8
#define UART2_SIM_CFG_WH_MASK 0x1ff
#define UART2_SIM_CFG_WH__SIM_GPIO_SEL_MASK 0x100
#define UART2_SIM_CFG_WH__CLK_MASK 0xf0
#define UART2_SIM_CFG_WH__SIM_CLK_ON_MASK 0x80
#define UART2_SIM_CFG_WH__SIM_CLK_TD8_SEL_MASK 0x40
#define UART2_SIM_CFG_WH__SIM_CLK_STOP_HI_MASK 0x20
#define UART2_SIM_CFG_WH__RESERVED_4_MASK 0x10
#define UART2_SIM_CFG_WH__MASK 0xf
#define UART2_SIM_CFG_WH__MASK_RX_MASK 0x8
#define UART2_SIM_CFG_WH__SWAP_D_MASK 0x4
#define UART2_SIM_CFG_WH__INV_D_MASK 0x2
#define UART2_SIM_CFG_WH__SIM_SEL_MASK 0x1
#define UART2_SIM_CFG_WH__SIM_CLK_OFF 0x0
//-----------------------------------------------------------------------------
// MSM MEMORY SPACE (CHIP_BASE + 0x3A0) to (CHIP_BASE + 0x3FC)
//
// SECTION UART2 READ REGISTERS
//-----------------------------------------------------------------------------
#define UART2_SR_RB 0x030003b4
#define UART2_SR_RB_MASK 0xff
#define UART2_SR_RB__HUNT_CHAR_MASK 0x80
#define UART2_SR_RB__RX_BREAK_MASK 0x40
#define UART2_SR_RB__PAR_FRAME_ERR_MASK 0x20
#define UART2_SR_RB__UART2_OVERRUN_MASK 0x10
#define UART2_SR_RB__TXEMT_MASK 0x8
#define UART2_SR_RB__TXRDY_MASK 0x4
#define UART2_SR_RB__RXFULL_MASK 0x2
#define UART2_SR_RB__RXRDY_MASK 0x1
#define UART2_RF_RB 0x030003b8
#define UART2_RF_RB_MASK 0xff
#define UART2_MISR_RB 0x030003bc
#define UART2_MISR_RB_MASK 0xff
#define UART2_ISR_RB 0x030003c0
#define UART2_ISR_RB_MASK 0x7f
#define UART2_ISR_RB__CURRENT_CTS_MASK 0x40
#define UART2_ISR_RB__DELTA_CTS_MASK 0x20
#define UART2_ISR_RB__RXLEV_MASK 0x10
#define UART2_ISR_RB__RXSTALE_MASK 0x8
#define UART2_ISR_RB__RXBREAK_MASK 0x4
#define UART2_ISR_RB__RXHUNT_MASK 0x2
#define UART2_ISR_RB__TXLEV_MASK 0x1
//-----------------------------------------------------------------------------
// MSM MEMORY SPACE CHIP_BASE to (CHIP_BASE + 0x400 to 0x4FC) UNUSED
//
// SECTION CDMA VOCODER WRITE REGISTERS
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// MSM MEMORY SPACE CHIP_BASE to (CHIP_BASE + 0x400 to 0x4FC) UNUSED W
//
// SECTION CDMA VOCODER READ REGISTERS
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// MSM MEMORY SPACE CHIP_BASE to (CHIP_BASE + 0x7FC)
//
// SECTION FM VOCODER WRITE REGISTERS
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// MSM MEMORY SPACE CHIP_BASE to (CHIP_BASE + 0x7FC)
//
// SECTION FM VOCODER READ REGISTERS
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// MSM MEMORY SPACE (CHIP_BASE + 0x500) to (CHIP_BASE + 0x5FC)
//
// SECTION DFM WRITE REGISTERS
//-----------------------------------------------------------------------------
#define DFM_INITIAL_WH 0x03000500
#define DFM_INITIAL_WH_MASK 0x1fe
#define DFM_INITIAL_WH__FREQ_BIAS_N_MASK 0x100
#define DFM_INITIAL_WH__IQ_FORMAT_MASK 0x40
#define DFM_INITIAL_WH__EN_DFM_TX_MASK 0x20
#define DFM_INITIAL_WH__CDMA_FM_SEL_MASK 0x10
#define DFM_INITIAL_WH__RES_DFM_UP_MASK 0x8
#define DFM_INITIAL_WH__MODE_DFM_360_MASK 0x4
#define DFM_INITIAL_WH__RES_DFM_360_MASK 0x2
#define DFM_DC_OFFSET_GAIN_WB 0x03000504
#define DFM_DC_OFFSET_GAIN_WB_MASK 0x3f
#define DFM_DC_OFFSET_GAIN_WB__Q_OFFSET_GAIN_MASK 0x38
#define DFM_DC_OFFSET_GAIN_WB__I_OFFSET_GAIN_MASK 0x7
#define DFM_AGC_REF_WB 0x03000508
#define DFM_AGC_REF_WB_MASK 0x1f
#define DFM_AGC_ACC_MIN_WB 0x0300050c
#define DFM_AGC_ACC_MIN_WB_MASK 0x3f
#define DFM_AGC_ACC_MAX_WB 0x03000510
#define DFM_AGC_ACC_MAX_WB_MASK 0x3f
#define DFM_AGC_GAIN_WB 0x03000514
#define DFM_AGC_GAIN_WB_MASK 0xff
#define DFM_AGC_GAIN_WB__AGC_LOOP_ATC_MASK 0xf0
#define DFM_AGC_GAIN_WB__AGC_LOOP_DTC_MASK 0xf
#define DFM_FREQ_LOOP_CONFIG_WB 0x03000518
#define DFM_FREQ_LOOP_CONFIG_WB_MASK 0x1f
#define DFM_FREQ_LOOP_CONFIG_WB__FREQ_CHIRP_EN_MASK 0x10
#define DFM_FREQ_LOOP_CONFIG_WB__FREQ_DITHER_EN_MASK 0x8
#define DFM_FREQ_LOOP_CONFIG_WB__FREQ_TRACK_GAIN_MASK 0x7
#define DFM_PDM_CONFIG_WB 0x0300051c
#define DFM_PDM_CONFIG_WB_MASK 0xff
#define DFM_PDM_CONFIG_WB__LOOP_STAT_SEL_MASK 0xc0
#define DFM_PDM_CONFIG_WB__FREQ_PDM_OE_MASK 0x20
#define DFM_PDM_CONFIG_WB__RXAGC_PDM_OE_MASK 0x10
#define DFM_PDM_CONFIG_WB__IQ_PDM_OE_MASK 0x8
#define DFM_PDM_CONFIG_WB__FREQ_PDM_POLARITY_MASK 0x4
#define DFM_PDM_CONFIG_WB__RXAGC_POLARITY_MASK 0x2
#define DFM_PDM_CONFIG_WB__DC_POLARITY_MASK 0x1
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