msm6000reg.h

在高通的手机平台下,一个下载手机.bin文件到手机的flash中的工具,包含PC端的程序代码和运行在基带处理器中的代码.

#define QP_TH1_RD_RH                                  0x03000124
#define QP_TH1_RD_RH_MASK                                  0x7ff
#define QP_Q_RD_RH                                    0x03000128
#define QP_Q_RD_RH_MASK                                    0x7ff
#define QP_TH2_RD_RH                                  0x0300012c
#define QP_TH2_RD_RH_MASK                                  0x7ff
#define TIME_INT_PHASE_RB                             0x03000130
#define TIME_INT_PHASE_RB_MASK                              0xff
#define TIME_INT_PHASE_RB__TIME_INT2_PHASE_MASK             0xf0
#define TIME_INT_PHASE_RB__TIME_INT1_PHASE_MASK              0xf
#define PC_ACC_RH                                     0x03000140
#define PC_ACC_RH_MASK                                    0xffff
#define NT_IO_ACC_RH                                  0x03000144
#define NT_IO_ACC_RH_MASK                                 0xffff
#define FPC_HISTORY_RH                                0x03000148
#define FPC_HISTORY_RH_MASK                               0xffff
#define RPC_HISTORY_RH                                0x0300014c
#define RPC_HISTORY_RH_MASK                               0xffff
#define CARRIER_FREQ_ERR_RD_LSB_RB                    0x03000164
#define CARRIER_FREQ_ERR_RD_LSB_RB_MASK                     0xff
#define CARRIER_FREQ_ERR_RD_MSB_RB                    0x03000168
#define CARRIER_FREQ_ERR_RD_MSB_RB_MASK                     0xff
#define I_OFFSET_RD_RH                                0x03000174
#define I_OFFSET_RD_RH_MASK                                0x1ff
#define Q_OFFSET_RD_RH                                0x03000178
#define Q_OFFSET_RD_RH_MASK                                0x1ff
#define RATCHET_BIT_DIS_RB                            0x03000190
#define RATCHET_BIT_DIS_RB_MASK                              0x3
#define RATCHET_BIT_DIS_RB__RATCHET_BIT_DOWN_MASK            0x2
#define RATCHET_BIT_DIS_RB__RATCHET_BIT_UP_MASK              0x1
#define RX_AGC_ADJ_RD_RH                              0x03000198
#define RX_AGC_ADJ_RD_RH_MASK                              0x1ff
#define TX_AGC_ADJ_RD_RH                              0x0300019c
#define TX_AGC_ADJ_RD_RH_MASK                              0x1ff
#define AGC_VALUE_RD_RH                               0x030001a0
#define AGC_VALUE_RD_RH_MASK                               0x3ff
#define CDMA_VGA_GAIN_RD_RH                           0x030001a4
#define CDMA_VGA_GAIN_RD_RH_MASK                           0x3ff
#define LNA_PA_RD_RB                                  0x030001ac
#define LNA_PA_RD_RB_MASK                                   0x3f
#define LNA_PA_RD_RB__LOAD_LINEARIZER_MASK                  0x20
#define LNA_PA_RD_RB__PA_R1_RD_MASK                         0x10
#define LNA_PA_RD_RB__PA_R0_RD_MASK                          0x8
#define LNA_PA_RD_RB__LNA_RANGE_RD_MASK                      0x7
#define LNA_FILT_RD_RH                                0x030001b0
#define LNA_FILT_RD_RH_MASK                                0x3ff
#define LNA_GAIN_RD_RH                                0x030001cc
#define LNA_GAIN_RD_RH_MASK                                0x1ff
#define TX_OPEN_LOOP_RD_RH                            0x030001d8
#define TX_OPEN_LOOP_RD_RH_MASK                            0x3ff
#define TX_GAIN_ADJ_RD_RH                             0x030001dc
#define TX_GAIN_ADJ_RD_RH_MASK                             0x1ff
#define TX_GAIN_CTL_RD_RH                             0x03000208
#define TX_GAIN_CTL_RD_RH_MASK                             0x3ff
#define AGC_TRK_LO_ADJ_RD_RH                          0x03000210
#define AGC_TRK_LO_ADJ_RD_RH_MASK                          0xfff
//-----------------------------------------------------------------------------
//  MSM MEMORY SPACE (CHIP_BASE + 0x220) to (CHIP_BASE + 0x2DC)
//
//  SECTION	MODULATOR WRITE REGISTERS
//-----------------------------------------------------------------------------
#define MOD_RESET_WB                                  0x03000220
#define MOD_RESET_WB_MASK                                   0xff
#define MOD_PCH_GAIN_WB                               0x03000224
#define MOD_PCH_GAIN_WB_MASK                                0xff
#define MOD_PCH_GAIN_WB__PCH_GAIN_MASK                      0xff
#define MOD_SCH_FCH_GAIN_WH                           0x03000228
#define MOD_SCH_FCH_GAIN_WH_MASK                          0xffff
#define MOD_SCH_FCH_GAIN_WH__SCH_GAIN_MASK                0xff00
#define MOD_SCH_FCH_GAIN_WH__FCH_GAIN_MASK                  0xff
#define FCH_PUNC_PATTERN_0_WH                         0x0300022c
#define FCH_PUNC_PATTERN_0_WH_MASK                        0xffff
#define FCH_PUNC_PATTERN_0_WH__RESERVED_15_8_MASK         0xff00
#define FCH_PUNC_PATTERN_0_WH__FCH_PUNCPATTERN_7_0_MASK        0xff
#define FCH_PUNC_PATTERN_1_WH                         0x03000230
#define FCH_PUNC_PATTERN_1_WH_MASK                        0xffff
#define FCH_PUNC_PATTERN_1_WH__FCH_PUNCPATTERN_23_8_MASK      0xffff
#define TX_2EARLY_PCG_EN_WB                           0x03000234
#define TX_2EARLY_PCG_EN_WB_MASK                            0x7f
#define TX_VERY_EARLY_FRAME_CTL_WH                    0x0300023c
#define TX_VERY_EARLY_FRAME_CTL_WH_MASK                    0xfff
#define TX_VERY_EARLY_FRAME_CTL_WH__VERY_EARLY_FRAME_ADV_MASK       0xffc
#define TX_VERY_EARLY_FRAME_CTL_WH__VERY_EARLY_FRAME_PER_MASK         0x3
#define I_PN_STATE_0_WB                               0x03000240
#define I_PN_STATE_0_WB_MASK                                0xff
#define I_PN_STATE_1_WB                               0x03000244
#define I_PN_STATE_1_WB_MASK                                0x7f
#define Q_PN_STATE_0_WB                               0x03000248
#define Q_PN_STATE_0_WB_MASK                                0xff
#define Q_PN_STATE_1_WB                               0x0300024c
#define Q_PN_STATE_1_WB_MASK                                0x7f
#define U_PN_STATE_0_WB                               0x03000250
#define U_PN_STATE_0_WB_MASK                                0xff
#define U_PN_STATE_1_WB                               0x03000254
#define U_PN_STATE_1_WB_MASK                                0xff
#define U_PN_STATE_2_WB                               0x03000258
#define U_PN_STATE_2_WB_MASK                                0xff
#define U_PN_STATE_3_WB                               0x0300025c
#define U_PN_STATE_3_WB_MASK                                0xff
#define U_PN_STATE_4_WB                               0x03000260
#define U_PN_STATE_4_WB_MASK                                0xff
#define U_PN_STATE_5_WB                               0x03000264
#define U_PN_STATE_5_WB_MASK                                0xff
#define U_PN_STATE_5_WB__BOZO_MASK                          0x80
#define U_PN_STATE_5_WB__U_PN_STATE_41_40_MASK               0x3
#define U_PN_MASK_0_WB                                0x03000268
#define U_PN_MASK_0_WB_MASK                                 0xff
#define U_PN_MASK_1_WB                                0x0300026c
#define U_PN_MASK_1_WB_MASK                                 0xff
#define U_PN_MASK_2_WB                                0x03000270
#define U_PN_MASK_2_WB_MASK                                 0xff
#define U_PN_MASK_3_WB                                0x03000274
#define U_PN_MASK_3_WB_MASK                                 0xff
#define U_PN_MASK_4_WB                                0x03000278
#define U_PN_MASK_4_WB_MASK                                 0xff
#define U_PN_MASK_5_WB                                0x0300027c
#define U_PN_MASK_5_WB_MASK                                  0x3
#define PA_WARMUP_WB                                  0x03000280
#define PA_WARMUP_WB_MASK                                   0xff
#define WSYM_STATE_WB                                 0x03000284
#define WSYM_STATE_WB_MASK                                  0xff
#define WSYM_STATE_WB__WSYM_CLK_WCHIP_MASK                  0xfc
#define WSYM_STATE_WB__WSYM_CLK_PN_MASK                      0x3
#define TXSYNC_ST_0_WB                                0x03000288
#define TXSYNC_ST_0_WB_MASK                                 0xff
#define TXSYNC_ST_1_WB                                0x0300028c
#define TXSYNC_ST_1_WB_MASK                                 0x3f
#define SYSFR_STATE_WB                                0x03000290
#define SYSFR_STATE_WB_MASK                                 0x3f
#define ENC_INT_ST_WB                                 0x03000294
#define ENC_INT_ST_WB_MASK                                  0x7f
#define ENC_INT_ST_WB__ENC_INT_PCG_MASK                     0x78
#define ENC_INT_ST_WB__ENC_INT_WSYM_MASK                     0x7
#define FCH_ENC_DATA_WH                               0x03000298
#define FCH_ENC_DATA_WH_MASK                              0xffff
#define FCH_CTL_WH                                    0x0300029c
#define FCH_CTL_WH_MASK                                   0xffff
#define FCH_CTL_WH__FCH_TX_TONE_EN_MASK                   0x8000
#define FCH_CTL_WH__RESERVED_14_12_MASK                   0x7000
#define FCH_CTL_WH__FCH_CRC_LENGTH_MASK                    0xf00
#define FCH_CTL_WH__RESERVED_7_MASK                         0x80
#define FCH_CTL_WH__FCH_CODE_RATE_MASK                      0x60
#define FCH_CTL_WH__FCH_ENC_RATE_SET_MASK                   0x10
#define FCH_CTL_WH__FCH_ENC_RATE_MASK                        0xc
#define FCH_CTL_WH__IS_95_C_MASK                             0x2
#define FCH_CTL_WH__IS95C_FCH_EN_MASK                        0x1
#define FCH_CRC_POLY_WH                               0x030002a0
#define FCH_CRC_POLY_WH_MASK                              0xffff
#define MOD_CLK_CTL_WH                                0x030002a8
#define MOD_CLK_CTL_WH_MASK                                0x1f8
#define MOD_CLK_CTL_WH__TX_CLK_INVERT_MASK                 0x100
#define MOD_CLK_CTL_WH__TX_CLKS_DISABLE_MASK                0x80
#define MOD_CLK_CTL_WH__VOC_REF_DISABLE_MASK                0x40
#define MOD_CLK_CTL_WH__CODEC_CTL_MASK                      0x38
#define MOD_MISC_CTL_WH                               0x030002ac
#define MOD_MISC_CTL_WH_MASK                              0x1fff
#define MOD_MISC_CTL_WH__PILOT_GATE_MASK                  0x1000
#define MOD_MISC_CTL_WH__FCH_EIGHTH_GATE_MASK              0x800
#define MOD_MISC_CTL_WH__HHO_PRMBL_MASK                    0x400
#define MOD_MISC_CTL_WH__IS95C_DCCH_EN_MASK                0x200
#define MOD_MISC_CTL_WH__IS95C_PCH_EN_MASK                 0x100
#define MOD_MISC_CTL_WH__IS95C_PCBIT_REG_EN_MASK            0x80
#define MOD_MISC_CTL_WH__TX_DATA_FORMAT_MASK                0x40
#define MOD_MISC_CTL_WH__IS95A_ACCESS_CH_MASK               0x20
#define MOD_MISC_CTL_WH__SYNC_CH_MASK                       0x10
#define MOD_MISC_CTL_WH__RESERVED_3_MASK                     0x8
#define MOD_MISC_CTL_WH__TX_BBA_MASK                         0x4
#define MOD_MISC_CTL_WH__PA_CTL_MASK                         0x3
#define FRAME_OFF_WB                                  0x030002b0
#define FRAME_OFF_WB_MASK                                   0xff
#define FRAME_OFF_WB__FWD_OFF_MASK                          0xf0
#define FRAME_OFF_WB__REV_OFF_MASK                           0xf
#define BTF_CTL_WB                                    0x030002b4
#define BTF_CTL_WB_MASK                                      0x1
#define BTF_CTL_WB__BTF_LOAD_MODE_MASK                       0x1
#define MOD_TEST_CTL_WH                               0x030002c0
#define MOD_TEST_CTL_WH_MASK                               0x3fe
#define MOD_TEST_CTL_WH__PA_STATE_TEST_DATA_MASK           0x300
#define MOD_TEST_CTL_WH__PA_STATE_TEST_EN_MASK              0x80
#define MOD_TEST_CTL_WH__TX_SPECTRAL_INVERSION_MASK         0x40
#define MOD_TEST_CTL_WH__RX_SPECTRAL_INVERSION_MASK         0x20
#define MOD_TEST_CTL_WH__TX_DATA_CTL_MASK                   0x10
#define MOD_TEST_CTL_WH__MASK_CTL_MASK                       0xc
#define MOD_TEST_CTL_WH__SET_IQ_HIGH_MASK                    0x2
#define TX_I_CLK_WB                                   0x030002c4
#define TX_I_CLK_WB_MASK                                    0xff
#define TX_DATA_TEST_WB                               0x030002c8
#define TX_DATA_TEST_WB_MASK                                0xff
#define PCH_PCBIT_DATA_WH                             0x030002cc
#define PCH_PCBIT_DATA_WH_MASK                            0xffff
#define MOD_ROTATOR_MAP_WB                            0x030002d4
#define MOD_ROTATOR_MAP_WB_MASK                             0xff
#define MOD_ROTATOR_MAP_WB__PASTATE11_MAP_MASK              0xc0
#define MOD_ROTATOR_MAP_WB__PASTATE10_MAP_MASK              0x30
#define MOD_ROTATOR_MAP_WB__PASTATE01_MAP_MASK               0xc
#define MOD_ROTATOR_MAP_WB__PASTATE00_MAP_MASK               0x3
#define IS95C_TX_PATN_WH                              0x030002d8
#define IS95C_TX_PATN_WH_MASK                             0xffff
//-----------------------------------------------------------------------------
//  MSM MEMORY SPACE (CHIP_BASE + 0x220) to (CHIP_BASE + 0x2DC)
//
//  SECTION	MODULATOR READ REGISTERS
//-----------------------------------------------------------------------------
#define MASK_DATA_RB                                  0x03000220
#define MASK_DATA_RB_MASK                                    0x1
#define MOD_STATUS_RB                                 0x03000224
#define MOD_STATUS_RB_MASK                                   0xf
#define MOD_STATUS_RB__SCH_ENCODING_MASK                     0x8