msm6000reg.h

在高通的手机平台下,一个下载手机.bin文件到手机的flash中的工具,包含PC端的程序代码和运行在基带处理器中的代码.

#define FFE_RSSI_FILT_GAIN_WB_MASK                          0xff
#define FFE_FN_RSSI_INIT_WB                           0x03000090
#define FFE_FN_RSSI_INIT_WB_MASK                            0xff
#define FFE_FN_BINARY_OFFSET_LOWER_WB                 0x03000094
#define FFE_FN_BINARY_OFFSET_LOWER_WB_MASK                  0xff
#define FFE_FN_BINARY_OFFSET_UPPER_WB                 0x03000098
#define FFE_FN_BINARY_OFFSET_UPPER_WB_MASK                  0x7f
#define FFE_FN_PN_I_MASK_LOWER_WB                     0x0300009c
#define FFE_FN_PN_I_MASK_LOWER_WB_MASK                      0xff
#define FFE_FN_PN_I_MASK_UPPER_WB                     0x030000a0
#define FFE_FN_PN_I_MASK_UPPER_WB_MASK                      0x7f
#define FFE_FN_PN_Q_MASK_LOWER_WB                     0x030000a4
#define FFE_FN_PN_Q_MASK_LOWER_WB_MASK                      0xff
#define FFE_FN_PN_Q_MASK_UPPER_WB                     0x030000a8
#define FFE_FN_PN_Q_MASK_UPPER_WB_MASK                      0x7f
#define FFE_FN_CODE_CHAN_ID_WB                        0x030000ac
#define FFE_FN_CODE_CHAN_ID_WB_MASK                         0xff
#define FFE_SLEW_VALUE_LOWER_WB                       0x030000b0
#define FFE_SLEW_VALUE_LOWER_WB_MASK                        0xff
#define FFE_SLEW_VALUE_MID_WB                         0x030000b4
#define FFE_SLEW_VALUE_MID_WB_MASK                          0xff
#define FFE_SLEW_VALUE_UPPER_WB                       0x030000b8
#define FFE_SLEW_VALUE_UPPER_WB_MASK                         0x7
#define FFE_PILOT_FILT_GAIN_WB                        0x030000bc
#define FFE_PILOT_FILT_GAIN_WB_MASK                         0xff
#define FFE_LOCK_THRESH_LOWER_WB                      0x030000c0
#define FFE_LOCK_THRESH_LOWER_WB_MASK                       0xff
#define FFE_LOCK_THRESH_UPPER_WB                      0x030000c4
#define FFE_LOCK_THRESH_UPPER_WB_MASK                       0xff
#define FFE_FN_PWR_THRESH_WB                          0x030000c8
#define FFE_FN_PWR_THRESH_WB_MASK                           0xff
#define FREQ_COMB_GAIN_WB                             0x030000cc
#define FREQ_COMB_GAIN_WB_MASK                              0xff
#define FFE_MERGE_DETECT_CTRL0_WH                     0x030000d0
#define FFE_MERGE_DETECT_CTRL0_WH_MASK                    0xffff
#define FFE_MERGE_DETECT_CTRL0_WH__TD_PAIR_MASK           0xff00
#define FFE_MERGE_DETECT_CTRL0_WH__RESERVED_7_5_MASK        0xe0
#define FFE_MERGE_DETECT_CTRL0_WH__THRESHOLD_MASK           0x1e
#define FFE_MERGE_DETECT_CTRL0_WH__FING_MERGE_ENABLE_MASK         0x1
#define FFE_MERGE_DETECT_CTRL1_WB                     0x030000d4
#define FFE_MERGE_DETECT_CTRL1_WB_MASK                      0x3f
#define FFE_MERGE_DETECT_CTRL1_WB__MERGE_CHECK_EN_MASK        0x3f
#define FN_CHAN_CTL_WB                                0x030000d8
#define FN_CHAN_CTL_WB_MASK                                 0xff
#define COMB_CHAN_CTL_WB                              0x030000dc
#define COMB_CHAN_CTL_WB_MASK                               0xff
#define POWER_COMB_CTL_WB                             0x030000e0
#define POWER_COMB_CTL_WB_MASK                              0xfc
#define POWER_COMB_CTL_WB__POWER_CTL_PCT_MASK               0x80
#define POWER_COMB_CTL_WB__PUNC_POS_SEL_MASK                0x40
#define POWER_COMB_CTL_WB__PC_EVEN_MASK                     0x20
#define POWER_COMB_CTL_WB__ERASE_EN_MASK                     0x8
#define POWER_COMB_CTL_WB__PWR_CTL_EN_MASK                   0x4
#define SYMB_COMB_CTL0_WH                             0x030000e4
#define SYMB_COMB_CTL0_WH_MASK                             0x3ff
#define SYMB_COMB_CTL0_WH__PN_ROLL_GEN_MASK                0x200
#define SYMB_COMB_CTL0_WH__PN_ROLL_CTL_MASK                0x100
#define SYMB_COMB_CTL0_WH__COMB_128_MASK                    0x80
#define SYMB_COMB_CTL0_WH__ULPN_OPTION_MASK                 0x40
#define SYMB_COMB_CTL0_WH__POSITION_MUX_MASK                0x20
#define SYMB_COMB_CTL0_WH__SYMB_COMB_FIN_EN_N_MASK          0x1e
#define SYMB_COMB_CTL0_WH__SLAM_EN_MASK                      0x1
#define SYMB_COMB_CTL1_WH                             0x030000e8
#define SYMB_COMB_CTL1_WH_MASK                             0xfff
#define SYMB_COMB_CTL1_WH__BETA_OVERWRITE_MASK             0x800
#define SYMB_COMB_CTL1_WH__DESKEW_OFFSET_MASK              0x700
#define SYMB_COMB_CTL1_WH__IQ_CAPTURE_EN_MASK               0x80
#define SYMB_COMB_CTL1_WH__OOK_REP_MASK                     0x40
#define SYMB_COMB_CTL1_WH__COMBINER_DISABLE_MASK            0x20
#define SYMB_COMB_CTL1_WH__EN_DDS_MASK                      0x10
#define SYMB_COMB_CTL1_WH__80MS_RESET_CTL_MASK               0xc
#define SYMB_COMB_CTL1_WH__SYMB_RATE_MASK                    0x2
#define DEM_PEEK_POKE_CTL_WB                          0x030000ec
#define DEM_PEEK_POKE_CTL_WB_MASK                            0xf
#define DEM_PEEK_POKE_CTL_WB__DEM_POKE_MASK                  0x8
#define DEM_PEEK_POKE_CTL_WB__DEM_PEEK_POKE_SEL_MASK         0x7
#define SYMB_COMB_FIFO_DEPTH_WB                       0x030000f0
#define SYMB_COMB_FIFO_DEPTH_WB_MASK                        0xff
#define SYMB_COMB_POS_DUMP_WB                         0x030000f4
#define SYMB_COMB_POS_DUMP_WB_MASK                           0x1
#define SYMB_COMB_POS_DUMP_WB__DUMP_MODE_MASK                0x1
#define SYMB_COMB_FREQ_ADJ_LOWER_WB                   0x030000f8
#define SYMB_COMB_FREQ_ADJ_LOWER_WB_MASK                    0xff
#define SYMB_COMB_FREQ_ADJ_UPPER_WB                   0x030000fc
#define SYMB_COMB_FREQ_ADJ_UPPER_WB_MASK                    0xff
#define SYMB_COMB_LONG_CODE_LD_0_WB                   0x03000100
#define SYMB_COMB_LONG_CODE_LD_0_WB_MASK                    0xff
#define SYMB_COMB_LONG_CODE_LD_1_WB                   0x03000104
#define SYMB_COMB_LONG_CODE_LD_1_WB_MASK                    0xff
#define SYMB_COMB_LONG_CODE_LD_2_WB                   0x03000108
#define SYMB_COMB_LONG_CODE_LD_2_WB_MASK                    0xff
#define SYMB_COMB_LONG_CODE_LD_3_WB                   0x0300010c
#define SYMB_COMB_LONG_CODE_LD_3_WB_MASK                    0xff
#define SYMB_COMB_LONG_CODE_LD_4_WB                   0x03000110
#define SYMB_COMB_LONG_CODE_LD_4_WB_MASK                    0xff
#define SYMB_COMB_LONG_CODE_LD_5_WB                   0x03000114
#define SYMB_COMB_LONG_CODE_LD_5_WB_MASK                     0x3
#define SYMB_COMB_LONG_CODE_MASK_0_WB                 0x03000118
#define SYMB_COMB_LONG_CODE_MASK_0_WB_MASK                  0xff
#define SYMB_COMB_LONG_CODE_MASK_1_WB                 0x0300011c
#define SYMB_COMB_LONG_CODE_MASK_1_WB_MASK                  0xff
#define SYMB_COMB_LONG_CODE_MASK_2_WB                 0x03000120
#define SYMB_COMB_LONG_CODE_MASK_2_WB_MASK                  0xff
#define SYMB_COMB_LONG_CODE_MASK_3_WB                 0x03000124
#define SYMB_COMB_LONG_CODE_MASK_3_WB_MASK                  0xff
#define SYMB_COMB_LONG_CODE_MASK_4_WB                 0x03000128
#define SYMB_COMB_LONG_CODE_MASK_4_WB_MASK                  0xff
#define SYMB_COMB_LONG_CODE_MASK_5_WB                 0x0300012c
#define SYMB_COMB_LONG_CODE_MASK_5_WB_MASK                   0x3
#define EPOCH_WR_WB                                   0x03000130
#define EPOCH_WR_WB_MASK                                    0xff
#define FFE_FN_SUP_CODE1_WB                           0x03000134
#define FFE_FN_SUP_CODE1_WB_MASK                            0x7f
#define DEM_FRAME_CTL_WB                              0x03000150
#define DEM_FRAME_CTL_WB_MASK                               0xff
#define DEM_FRAME_CTL_WB__SET_ROLL_SYNC_MASK                0x80
#define DEM_FRAME_CTL_WB__FRAME_SYNC_BYPASS_MASK            0x40
#define DEM_FRAME_CTL_WB__FRAME_OFF_MASK                    0x3f
#define DEM_CTL_WB                                    0x03000154
#define DEM_CTL_WB_MASK                                     0x3f
#define DEM_CTL_WB__DSP_BYPASS_MASK                         0x20
#define DEM_CTL_WB__DSP_SUP_OFF_MASK                        0x10
#define DEM_CTL_WB__MAC_EN_MASK                              0x8
#define DEM_CTL_WB__Q_CHAN_OFF_MASK                          0x4
#define DEM_CTL_WB__I_CHAN_OFF_MASK                          0x2
#define DEM_CTL_WB__SYNC_BYPASS_MASK                         0x1
#define OOK_CTL_WH                                    0x03000158
#define OOK_CTL_WH_MASK                                    0x3ff
#define OOK_CTL_WH__OOK_POSITION_MASK                      0x3fe
#define OOK_CTL_WH__OOK_EN_MASK                              0x1
#define DEM_CH2_SPR_WB                                0x0300015c
#define DEM_CH2_SPR_WB_MASK                                 0x1f
#define FREQ_COMB_CTL_WB                              0x03000160
#define FREQ_COMB_CTL_WB_MASK                               0x7c
#define FREQ_COMB_CTL_WB__CROSS_MODE_MASK                   0x60
#define FREQ_COMB_CTL_WB__TRK_LO_ADJ_EN_MASK                0x10
#define FREQ_COMB_CTL_WB__TRK_LO_ADJ_POLARITY_MASK           0x8
#define FREQ_COMB_CTL_WB__CARRIER_FREQ_TRACK_EN_MASK         0x4
#define CARRIER_FREQ_ERR_WR_LSB_WB                    0x03000164
#define CARRIER_FREQ_ERR_WR_LSB_WB_MASK                     0xff
#define CARRIER_FREQ_ERR_WR_MSB_WB                    0x03000168
#define CARRIER_FREQ_ERR_WR_MSB_WB_MASK                     0xff
//the following 2 reg's address is discontinuous from above
#define COMB_COUNT_INCR_UPPER_WB                      0x030002e4
#define COMB_COUNT_INCR_UPPER_WB_MASK                        0xf
#define COMB_COUNT_INCR_LOWER_WB                      0x030002e8
#define COMB_COUNT_INCR_LOWER_WB_MASK                     0xffff
//-----------------------------------------------------------------------------
//  MSM MEMORY SPACE CHIP_BASE to (CHIP_BASE + 0x21C)
//
//  SECTION	DEMODULATOR READ REGISTERS
//-----------------------------------------------------------------------------
#define SRCH_DMA_ERROR_RB                             0x03000004
#define SRCH_DMA_ERROR_RB_MASK                               0x1
#define SRCH_POSITION_LOW_RH                          0x03000030
#define SRCH_POSITION_LOW_RH_MASK                         0xffff
#define SRCH_POSITION_HIGH_RB                         0x03000038
#define SRCH_POSITION_HIGH_RB_MASK                           0x3
#define SRCH_DMA_DATA_RH                              0x0300003c
#define SRCH_DMA_DATA_RH_MASK                             0xffff
#define SRCH_MAX_ENERGY_RH                            0x03000044
#define SRCH_MAX_ENERGY_RH_MASK                           0xffff
#define SRCH_MAX_INDEX_RH                             0x0300004c
#define SRCH_MAX_INDEX_RH_MASK                            0xffff
#define DEM_DMEM_STATUS_RH                            0x03000054
#define DEM_DMEM_STATUS_RH_MASK                              0x7
#define DEM_DMEM_DOUT_RH                              0x03000058
#define DEM_DMEM_DOUT_RH_MASK                             0xffff
#define DEM_DSP_INT_WORD_RH                           0x0300005c
#define DEM_DSP_INT_WORD_RH_MASK                          0xffff
#define RXDSP_OP_SPARE_RH                             0x03000060
#define RXDSP_OP_SPARE_RH_MASK                            0xffff
#define FN_LOCK_RSSI_RH                               0x0300008c
#define FN_LOCK_RSSI_RH_MASK                              0xffff
#define FN_POSITION_LOWER_RH                          0x030000b0
#define FN_POSITION_LOWER_RH_MASK                         0xffff
#define FN_POSITION_UPPER_RB                          0x030000b8
#define FN_POSITION_UPPER_RB_MASK                            0x3
#define EPOCH_TIMER_LOWER_RH                          0x030000bc
#define EPOCH_TIMER_LOWER_RH_MASK                         0xffff
#define EPOCH_TIMER_UPPER_RH                          0x030000c0
#define EPOCH_TIMER_UPPER_RH_MASK                            0x3
#define SYMB_COMB_STATUS0_RB                          0x030000e4
#define SYMB_COMB_STATUS0_RB_MASK                           0x7f
#define SYMB_COMB_STATUS0_RB__LOCK_STATE_F3_MASK            0x40
#define SYMB_COMB_STATUS0_RB__LOCK_STATE_F2_MASK            0x20
#define SYMB_COMB_STATUS0_RB__LOCK_STATE_F1_MASK            0x10
#define SYMB_COMB_STATUS0_RB__LOCK_STATE_F0_MASK             0x8
#define SYMB_COMB_FINE_POSITION_RB                    0x030000e8
#define SYMB_COMB_FINE_POSITION_RB_MASK                      0xf
#define SYMB_COMB_POSITION2_LOWER_RB                  0x030000f8
#define SYMB_COMB_POSITION2_LOWER_RB_MASK                   0xff
#define SYMB_COMB_POSITION2_UPPER_RB                  0x030000fc
#define SYMB_COMB_POSITION2_UPPER_RB_MASK                   0xff
#define SYMB_COMB_LONG_CODE_RD_0_RB                   0x03000100
#define SYMB_COMB_LONG_CODE_RD_0_RB_MASK                    0xff
#define SYMB_COMB_LONG_CODE_RD_1_RB                   0x03000104
#define SYMB_COMB_LONG_CODE_RD_1_RB_MASK                    0xff
#define SYMB_COMB_LONG_CODE_RD_2_RB                   0x03000108
#define SYMB_COMB_LONG_CODE_RD_2_RB_MASK                    0xff
#define SYMB_COMB_LONG_CODE_RD_3_RB                   0x0300010c
#define SYMB_COMB_LONG_CODE_RD_3_RB_MASK                    0xff
#define SYMB_COMB_LONG_CODE_RD_4_RB                   0x03000110
#define SYMB_COMB_LONG_CODE_RD_4_RB_MASK                    0xff
#define SYMB_COMB_LONG_CODE_RD_5_RB                   0x03000114
#define SYMB_COMB_LONG_CODE_RD_5_RB_MASK                     0x3
#define QP_I_RD_RH                                    0x03000120
#define QP_I_RD_RH_MASK                                    0x7ff