📄 clkregim.h
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#ifndef CLKREGIM_H
#define CLKREGIM_H
/*===========================================================================
C L O C K R E G I M E I N T E R N A L H E A D E R F I L E
DESCRIPTION
This header file contains all the internal definitions used by the
DMSS clock regime services.
Copyright (c) 1999-2002 by QUALCOMM, Incorporated. All Rights Reserved.
===========================================================================*/
/*===========================================================================
EDIT HISTORY FOR FILE
This section contains comments describing changes made to this file.
Notice that changes are listed in reverse chronological order.
$Header: L:/src/asw/MSM6000/vcs/clkregim.h_v 1.4 20 Mar 2002 19:57:20 hromero $
when who what, where, why
-------- --- ----------------------------------------------------------
02/21/02 rmd The macros bellow were removed because with the PM60X0,
they are not longer necessary.
CLOCK_SWITCH_SBI_CLK_TO_SLEEP( )
CLOCK_SWITCH_SBI_CLK_TO_TCXO( )
02/12/02 hjr Renamed clk_regime_block_type to clk_regime_sel_src_type and
renamed each enumed to match rf driver. Prototypes for
clk_rgm_sel and clk_rgm_force were removed since we were no
longer support those interfaces
05/09/01 rmd Removed old micro clock switching code.
03/04/01 rmd Created clk_regime_uP_sleep() function so that the MSM5105
and the MSM5100 put the ARM to sleep with the same function
call.
03/04/01 rmd Created clk_regime_set_mclk_sleep(). This function
takes care of turning off TCXO, putting the MSM to sleep
and restoring TCXO after the MSM wakes up.
03/09/01 djd Added macro CLOCK_SWITCH_ENABLE_GP_TIMER().
02/12/01 rmd Moved mclk switching code to mclk_XXXX.c (XXXX depends on target, eg:
mclk_6000.c).
12/04/00 rmd Modified clk_rgm_sel() so that it recognizes which clk source
we want to initialize depending on the parameters pass.
11/23/00 et changed clk_regime_enable/disable and added clk_rgm_force and clk_rgm_sel
for the new clk API changes
11/22/00 rmd Created clk_regime_switch_mclk_to_tcxo() so that we can switch MCLK
source from 4/3 TCXO to TCXO just before we get to download mode.
11/21/00 rmd Added support to 4/3 TCXO. Moved clk_regime_chipxn_clk_init()
from the boot code to the clk regime code.
11/03/00 rmd Fixed CLOCK_SWITCH_SBI_CLK_TO_SLEEP Macro. Updated MSM_CLK_CTL7
bit definitions.
10/17/00 rmd Removed CLOCK_SWITCH_SET_WAIT_STATES_TXCO Macro and placed
corresponding code inside boot_hw_mem_wt_st_cfg() which is
located inside the boot code.
09/07/00 jcw fixed compile error in 5105 changes.
08/28/00 et changed the clock regimes to corrispond to the MSM5105 clkregim
10/06/00 dsb Added preliminary support for clk regime "set 1" via
MSMHW_HAS_CLK_RGM_REG_SET1. This is the added ability
of turning on/off clk regimes in another "set" of enable &
reset (and optionally override) registers. Moved
target-dependent clk regime definitions to a separate
file, included by the CLKRGM_H make macro.
04/20/00 rp Added clk_regime_usb_xtal_on() and clk_usb_xtal_off()
under FEATURE_USB.
04/12/00 sm Added FEATURE_FAST_QDSP
01/20/00 jc Added support for FEATURE_PM1000_SCI
01/20/00 mk Added Main PLL ON/OFF control functions.
11/12/99 mk Added FEATURE_SEARCH2 support.
10/07/99 mk Added Codec PLL ON/OFF control functions.
09/12/99 mk Added MSM3100 REV2(3), deleted MSM3000 support.
07/15/99 mk New complete MSM3100 clock regime defs, deleted 10/20 MHz
TCXO clock featurization.
06/15/99 spf Added 10/20MHz TCXO clock featurization.
05/12/99 mk Started MSM3100, deleted MSM2300(10) support.
===========================================================================*/
#include "comdef.h" /* Definitions for byte, word, etc. */
#include "target.h" /* Target specific definitions */
#include "msm.h"
#include "boothw.h"
#ifdef CLKRGM_H
#include CLKRGM_H
#else
#error Must Specify /DCLKRGM_H=CLKRGM_xxxx.H on the compile line
#endif
#ifdef MCLK_H
#include MCLK_H
#else
#error Must Specify /MCLK_H=MCLK_xxxx.H on the compile line
#endif
/*===========================================================================
DEFINITIONS AND DECLARATIONS FOR MODULE
This section contains definitions for constants, macros, types, variables
and other items needed by this module.
===========================================================================*/
typedef enum {
CLK_RGM_SRC_SEL_UART1 = 0x0,
CLK_RGM_SRC_SEL_DEC,
CLK_RGM_SRC_SEL_RXSAMPLE,
CLK_RGM_SRC_SEL_RXFRONT,
CLK_RGM_SRC_SEL_RXMOD,
CLK_RGM_NUM_BLKS
} clk_regime_src_sel_type;
/*===========================================================================
FUNCTION CLK_REGIME_SEL_CLK_SRC
DESCRIPTION
Select a clock source for a specified HW block.
DEPENDENCIES
Source selected must be oscillating and stable.
RETURN VALUE
None
SIDE EFFECTS
None.
===========================================================================*/
void clk_regime_sel_clk_src
(
clk_regime_src_sel_type block,
/* Change the clock source of this HW block */
dword src
/* Mask value indicating clock source to switch to */
);
typedef enum {
CLK_RXCX8_BYPASS_M = (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x0400),
CLK_RGM_DEC_M = (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x0800), /* DEC DEINT Clock Regime */
CLK_RGM_GEN_M = (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x0001), /* Timetick, Ringer, PDM1,2, YAMN1 */
CLK_RGM_UART_M = (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x0002), /* UART, HKADC Intf */
CLK_RGM_CDMA_TX_M = (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x0004), /* Modulator, Interleaver */
CLK_RGM_CDMA_RX8_M = (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x0008), /* Searcher, Combiner, FFE */
CLK_RGM_DFM_M = (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x0010), /* DFM Core, PDMs */
CLK_RGM_COD_M = (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x0020), /* PCM CODEC Intf */
CLK_RGM_VOC_M = (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x0040), /* Vocoder */
CLK_RGM_SBI_M = (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x0100), /* SBI Intf */
CLK_RGM_CDMA_RXDSP_M = (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x0200), /* Decoder Deinterleaver DemodDSP */
CLK_RGM_COD_CORE_M = (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x1000), /* CODEC Core */
CLK_RGM_RXFRONT_M = (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x2000), /* RXFRONT */
CLK_RGM_CDMA_AGC_M = (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x4000), /* CDMA AGC Rx PDMs */
CLK_RGM_CDMA_PDM_M = (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x8000), /* Rx and Tx PDMs */
RXCX8_MICRO_BYPASS_M = MSM_CLK_CTL1_WH__RXCX8_BYPASS_MASK,
CLK_RGM_CHIPX8_M = ( CLK_RGM_CDMA_TX_M |
CLK_RGM_CDMA_RX8_M |
CLK_RGM_CDMA_RXDSP_M |
CLK_RGM_CDMA_AGC_M |
CLK_RGM_CDMA_PDM_M ),
CLK_RGM_CDMA_RX_M = ( CLK_RGM_CDMA_RX8_M | \
CLK_RGM_CDMA_RXDSP_M | \
CLK_RGM_CDMA_AGC_M | \
CLK_RGM_CDMA_PDM_M ),
VOC_CLK_DIV_DIV1_M = (((MSM_CLK_CTL5_WH & 0xffff) << 16) | MSM_CLK_CTL5_WH__VOC_CLK_DIV_DIV1),
QDSP2_CODEC_EN_N_M = (((MSM_CLK_CTL5_WH & 0xffff) << 16) | CODEC_CTL_WH__QDSP2_CODEC_CTL_EN_MASK),
} clk_regime_type;
/*===========================================================================
FUNCTION CLK_REGIME_CHIPXN_CLK_INIT
===========================================================================*/
void clk_regime_chipxn_clk_init( void );
/*===========================================================================
FUNCTION CLK_REGIME_INIT
===========================================================================*/
extern void clk_regime_init ( void );
/*===========================================================================
FUNCTION CLK_REGIME_PLL_ON
===========================================================================*/
void clk_regime_pll_on ( void );
/*===========================================================================
FUNCTION CLK_REGIME_PLL_OFF
===========================================================================*/
void clk_regime_pll_off ( void );
/*===========================================================================
FUNCTION CLK_REGIME_CPLL_ON
===========================================================================*/
#ifdef FEATURE_CPLL
void clk_regime_cpll_on ( void );
#else
#define clk_regime_cpll_on()
#endif /*FEATURE_CPLL*/
/*===========================================================================
FUNCTION CLK_REGIME_CPLL_OFF
===========================================================================*/
#ifdef FEATURE_CPLL
void clk_regime_cpll_off ( void );
#else
#define clk_regime_cpll_off()
#endif /*FEATURE_CPLL*/
/*===========================================================================
FUNCTION CLK_REGIME_ENABLE
===========================================================================*/
extern void clk_regime_enable
(
clk_regime_type regime_mask
);
#if defined(MSMHW_HAS_CLK_RGM_REG_SET1)
extern void clk_regime_set1_enable
(
word regime_mask
);
#endif
/*===========================================================================
FUNCTION CLK_REGIME_ENABLE_MISC
===========================================================================*/
extern void clk_regime_misc_enable
(
clk_regime_misc_type regime_bit
);
/*===========================================================================
FUNCTION CLK_REGIME_DISABLE
===========================================================================*/
extern void clk_regime_disable
(
clk_regime_type regime_mask
);
#if defined(MSMHW_HAS_CLK_RGM_REG_SET1)
extern void clk_regime_set1_disable
(
word regime_mask
);
#endif
/*===========================================================================
FUNCTION CLK_REGIME_DISABLE_MISC
===========================================================================*/
extern void clk_regime_misc_disable
(
clk_regime_misc_type regime_bit
);
/*===========================================================================
FUNCTION CLK_REGIME_SET_MCLK_SLEEP()
===========================================================================*/
void clk_regime_set_mclk_sleep(void);
/*===========================================================================
FUNCTION CLK_REGIME_UP_SLEEP
===========================================================================*/
void clk_regime_uP_sleep(void);
/*===========================================================================
FUNCTION CLK_REGIME_RESET
===========================================================================*/
extern void clk_regime_reset
(
word regime_mask
);
#if defined(MSMHW_HAS_CLK_RGM_REG_SET1)
extern void clk_regime_set1_reset
(
word regime_mask
);
#endif
#ifdef FEATURE_FAST_QDSP
/*===========================================================================
FUNCTION CLK_REGIME_FAST_QDSP
===========================================================================*/
extern void clk_regime_fast_qdsp
(
boolean enabled
);
#endif /* FEATURE_FAST_QDSP */
#ifdef FEATURE_USB
#error code not present
#endif
#ifdef FEATURE_USB
#error code not present
#endif
#ifdef FEATURE_UP_CLOCK_SWITCHING
extern word tramp_int_mask_0;
extern word tramp_int_mask_1;
/*
** Wait states for RAM1, RAM2, ROM1, ROM2 if ARM sourced with sleep clock
*/
#define SLEEP_RAM1_WAIT 0x1
#define SLEEP_RAM2_WAIT 0x1
#define SLEEP_ROM1_WAIT 0x1
#define SLEEP_ROM2_WAIT 0x1
/* Preset GP timer to 1.25ms */
#define CLOCK_SWITCH_SET_TIMER( ) \
MSM_OUTH(DMOD_INT_CLEAR_0, 0x01); \
MSM_OUT(GPTIMER_CTL_WB, 0x00); \
MSM_OUT(GPTIMER_COUNT_WB, 0x00); \
MSM_OUT(GPTIMER_COUNT_WB, 0x01); \
MSM_OUT(GPTIMER_CTL_WB, 0x01)
/* Powerdown with TCXO */
#define CLOCK_SWITCH_POWERDOWN_UP_TCXO_CLOCK( ) \
outp(UP_CLK_CTL1_WB, UP_CLK_CTL1_WB__UP_CLK_SRC_TCXO | 0x01), \
outp(UP_CLK_CTL1_WB, UP_CLK_CTL1_WB__UP_CLK_SRC_TCXO)
/* Powerdown with Sleep clock (32KHz) */
#define CLOCK_SWITCH_POWERDOWN_UP_SLEEP_CLOCK( ) \
outp(UP_CLK_CTL1_WB, UP_CLK_CTL1_WB__UP_CLK_SRC_SLEEP_XTAL_IN | 0x01), \
outp(UP_CLK_CTL1_WB, UP_CLK_CTL1_WB__UP_CLK_SRC_SLEEP_XTAL_IN)
/* Enable General clock regime for GP Timer.
NOTE: This macro is specifically optimized for waking up from sleep, when
interrupts are disabled. clk_regime_enable() should be used in all other
cases.
*/
#define CLOCK_SWITCH_ENABLE_GP_TIMER( ) \
MSM_OUTHM_NO_INTLOCK( MSM_CLK_CTL2_WH, CLK_RGM_GEN_M & 0xffff, CLK_RGM_CLEAR ); \
MSM_OUTHM_NO_INTLOCK( MSM_CLK_CTL1_WH, CLK_RGM_GEN_M & 0xffff, CLK_RGM_ENABLE )
/* Setup Sleep clock (32KHz) based memory wait states */
#define CLOCK_SWITCH_SET_WAIT_STATES_SLEEP( ) \
outpw (MEMORY_WAIT1_WH, (ROM2_BASE<<8) | (SLEEP_ROM1_WAIT << 4) | \
(SLEEP_ROM2_WAIT) ); \
outpw (MEMORY_WAIT2_WH, (RAM2_BASE<<8) | (SLEEP_RAM1_WAIT << 4) | \
(SLEEP_RAM2_WAIT) )
#endif /* FEATURE_UP_CLOCK_SWITCHING */
#endif /* CLKREGIM_H */
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