📄 msm6000redefs.h
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START DLOAD2I.H SIOG2.C
===========================================================================*/
#define UART_MR1 UART_MR1_WB
#define UART_TXWAT UART_TFWR_WB
#define UART_RXWAT UART_RFWR_WB
#define UART_MR2 UART_MR2_WB
#define UART_SR UART_SR_RB
#define UART_CSR UART_CSR_WB
#define UART_RFIFO UART_RF_RB
#define UART_TFIFO UART_TF_WB
#define UART_MISR UART_MISR_RB
#define UART_CR UART_CR_WB
#define UART_ISR UART_ISR_RB
#define UART_IMR UART_IMR_WB
#define UART_IPR UART_IPR_WB
#define UART_HCR UART_HCR_WB
#define UART_MVR UART_MREG_WB
#define UART_NVR UART_NREG_WB
#define UART_DVR UART_DREG_WB
#define UART_MNDR UART_MNDREG_WB
#define MSMU_MR1 UART_MR1_WB /* Mode Register 1 */
#define MSMU_TFWR UART_TFWR_WB /* TX FIFO Watermark Register */
#define MSMU_RFWR UART_RFWR_WB /* RX FIFO watermark Register */
#define MSMU_IPR UART_IPR_WB /* Interrupt Programming Register */
#define MSMU_MR2 UART_MR2_WB /* Mode Register 2 */
#define MSMU_SR UART_SR_RB /* Status Register */
#define MSMU_CSR UART_CSR_WB /* Clock Select Register */
#define MSMU_RF UART_RF_RB /* Receive FIFO */
#define MSMU_TF UART_TF_WB /* Transmit FIFO */
#define MSMU_MISR UART_MISR_RB /* Masked Interrupt Status Register */
#define MSMU_CR UART_CR_WB /* Command Register */
#define MSMU_ISR UART_ISR_RB /* Interrupt Status Register */
#define MSMU_IMR UART_IMR_WB /* Interrupt Mask Register */
#define MSMU_HCR UART_HCR_WB /* Hunt Character Register */
#define MSMU_MVR UART_MREG_WB /* M Value Register */
#define MSMU_NVR UART_NREG_WB /* N Value Register */
#define MSMU_DVR UART_DREG_WB /* D Value Register */
#define MSMU_MNDR UART_MNDREG_WB /* Extra Value Register */
#define MSMU_IRDA UART_IRDA_WB /* UART IRDA Register */
/* These are definitions for second UART */
#define UART2_MR1 UART2_MR1_WB
#define UART2_MR2 UART2_MR2_WB
#define UART2_SR UART2_SR_RB
#define UART2_CSR UART2_CSR_WB
#define UART2_RFIFO UART2_RF_RB
#define UART2_TFIFO UART2_TF_WB
#define UART2_MISR UART2_MISR_RB
#define UART2_CR UART2_CR_WB
#define UART2_ISR UART2_ISR_RB
#define UART2_IMR UART2_IMR_WB
#define UART2_IPR UART2_IPR_WB
#define UART2_TXWAT UART2_TFWR_WB
#define UART2_RXWAT UART2_RFWR_WB
#define UART2_HCR UART2_HCR_WB
#define UART2_MVR UART2_MREG_WB
#define UART2_NVR UART2_NREG_WB
#define UART2_DVR UART2_DREG_WB
#define UART2_MNDR UART2_MNDREG_WB
#define MSMU2_MR1 UART2_MR1_WB /* Mode Register 1 */
#define MSMU2_MR2 UART2_MR2_WB /* Mode Register 2 */
#define MSMU2_SR UART2_SR_RB /* Status Register */
#define MSMU2_CSR UART2_CSR_WB /* Clock Select Register */
#define MSMU2_RF UART2_RF_RB /* Receive FIFO */
#define MSMU2_TF UART2_TF_WB /* Transmit FIFO */
#define MSMU2_MISR UART2_MISR_RB /* Masked Interrupt Status Register */
#define MSMU2_CR UART2_CR_WB /* Command Register */
#define MSMU2_ISR UART2_ISR_RB /* Interrupt Status Register */
#define MSMU2_IMR UART2_IMR_WB /* Interrupt Mask Register */
#define MSMU2_IPR UART2_IPR_WB /* Interrupt Programming Register */
#define MSMU2_TFWR UART2_TFWR_WB /* TX FIFO Watermark Register */
#define MSMU2_RFWR UART2_RFWR_WB /* RX FIFO watermark Register */
#define MSMU2_HCR UART2_HCR_WB /* Hunt Character Register */
#define MSMU2_MVR UART2_MREG_WB /* M Value Register */
#define MSMU2_NVR UART2_NREG_WB /* N Value Register */
#define MSMU2_DVR UART2_DREG_WB /* D Value Register */
#define MSMU2_MNDR UART2_MNDREG_WB /* Extra Value Register */
#define MSMU2_IRDA UART2_IRDA_WB /* UART IRDA Register */
/*===========================================================================
END DLOAD2I.H SIOG2.C
===========================================================================*/
/*===========================================================================
START RUIM.H
===========================================================================*/
#define RUIM_CLK_MDIV_LSB YAMN1_CLK_MDIV_LSB_WB
#define RUIM_CLK_MDIV_MSB YAMN1_CLK_MDIV_MSB_WB
#define RUIM_CLK_NDIV_LSB YAMN1_CLK_NDIV_LSB_WB
#define RUIM_CLK_NDIV_MSB YAMN1_CLK_NDIV_MSB_WB
#define RUIM_CLK_DUTY_LSB YAMN1_CLK_DUTY_LSB_WB
#define RUIM_CLK_DUTY_MSB YAMN1_CLK_DUTY_MSB_WB
/*===========================================================================
START ADC.H
===========================================================================*/
#define ADC_CNTRL_STAT ADC_RESET_WB
#define ADC_DATA ADC_DATA_WR_WB
/*===========================================================================
END ADC.H
===========================================================================*/
/*===========================================================================
START BIO.H
===========================================================================*/
#define BIO_PORT_7_OUT 0x02800000 // (P_PCS0_IO + 0x3E)
/* All GPIO_INTs(0:4) have been mapped from GPIO_INT_OUT to GPIO_0 in MSM3100 */
#define DMOD_GPIO_INT_OUT GPIO_INT_OUT_0_WH
#define DMOD_GPIO_INT_TSEN GPIO_INT_TSEN_0_WH
#define DMOD_GPIO_INT_IN GPIO_INT_IN_0_RH
/* All of GPIO_OUT_1 has been mapped to GPIO_0 in MSM3100 */
#define ENC_GPIO_0_OUT GPIO_INT_OUT_0_WH
#define ENC_GPIO_0_TSEN GPIO_INT_TSEN_0_WH
#define ENC_GPIO_0_IN GPIO_INT_IN_0_RH
/* Half of GPIO_OUT_2 has been mapped to GPIO_0 and half to GPIO_1 in MSM3100 */
/* I arbitrarily assigned GPIO_0 to ENC_GPIO_1 instead of assigning GPIO_1 */
#define ENC_GPIO_1_OUT GPIO_INT_OUT_0_WH
#define ENC_GPIO_1_TSEN GPIO_INT_TSEN_0_WH
#define ENC_GPIO_1_IN GPIO_INT_IN_0_RH
/* All of GPIO_OUT_3 has been mapped to GPIO_1 in MSM3100 */
#define DEC_GPIO_0_OUT GPIO_INT_OUT_1_WH
#define DEC_GPIO_0_TSEN GPIO_INT_TSEN_1_WH
#define DEC_GPIO_0_IN GPIO_INT_IN_1_RH
/* All of GPIO_OUT_4 has been mapped to GPIO_1 in MSM3100 */
#define DEC_GPIO_1_OUT GPIO_INT_OUT_1_WH
#define DEC_GPIO_1_TSEN GPIO_INT_TSEN_1_WH
#define DEC_GPIO_1_IN GPIO_INT_IN_1_RH
/* All of GPIO_OUT_0 except GPIO5 have been mapped to GPIO_2 in MSM3100 */
#define DMOD_GPIO_OUT GPIO_INT_OUT_2_WH
#define DMOD_GPIO_TSEN GPIO_INT_TSEN_2_WH
#define DMOD_GPIO_IN GPIO_INT_IN_2_RH
/*===========================================================================
END BIO.H
===========================================================================*/
/*===========================================================================
START INTERRUPT ALIAS
===========================================================================*/
#define DMOD_INT_CLEAR_0 INT_CLEAR_0_WH
#define DMOD_INT_MASK_0 IRQ_MASK_0_WH
#define DMOD_INT_CLEAR_1 INT_CLEAR_1_WH
#define DMOD_INT_MASK_1 IRQ_MASK_1_WH
#if defined(MSMHW_GROUP_INT_FOR_ALL_GPIO)
#define DMOD_POLARITY INT_POLARITY_3_WB
#else
#define DMOD_POLARITY INT_POLARITY_0_WH
#endif
#define GPIO_INT_MASK_0 GPIO_INT_MASK_0_WH
#define GPIO_INT_MASK_1 GPIO_INT_MASK_1_WH
#define GPIO_INT_MASK_2 GPIO_INT_MASK_2_WH
#define GPIO_INT_MASK_3 GPIO_INT_MASK_3_WB
#define GPIO_INT_CLEAR_0 GPIO_INT_CLEAR_0_WH
#define GPIO_INT_CLEAR_1 GPIO_INT_CLEAR_1_WH
#define GPIO_INT_CLEAR_2 GPIO_INT_CLEAR_2_WH
#define GPIO_INT_CLEAR_3 GPIO_INT_CLEAR_3_WH
/*===========================================================================
START SEARCHER ALIASES
===========================================================================*/
#define SYMB_COMB_CTL1_WH__LOCK_RSSI_EXT_RANGE_MASK SYMB_COMB_CTL1_WH__OOK_REP_MASK
#define FFE_MERGE_DETECT_CTRL0_WH__MASTER_OF_FN_MASK FFE_MERGE_DETECT_CTRL0_WH__TD_PAIR_MASK
#define SYMB_COMB_CTL0_WH__SYMB_COMB_FIN_EN_n_MASK SYMB_COMB_CTL0_WH__SYMB_COMB_FIN_EN_N_MASK
#define VD_MODE_WB__INTMODE_MASK VD_MODE_WB__INITMODE_MASK
#define Fn_CH0_QOF_SEL_WH FN_CH0_QOF_SEL_WH
#define Fn_CH1_QOF_SEL_WH FN_CH1_QOF_SEL_WH
#define Fn_OTD_CFG_WB FN_OTD_CFG_WB
#define SEARCH_STATUS_DUMP_CTL_WB SRCH_STATUS_DUMP_CTL_WB
#define SEARCH_STATUS_DUMP_CTL_WB__SEARCH2_DUMP_EN_MASK SRCH_STATUS_DUMP_CTL_WB__SEARCHER2_DUMP_EN_MASK
#define SEARCH_STATUS_DUMP_CTL_WB__SEARCH1_DUMP_EN_MASK SRCH_STATUS_DUMP_CTL_WB__SEARCHER1_DUMP_EN_MASK
#define SEARCH_STATUS_DUMP_CTL_WB SRCH_STATUS_DUMP_CTL_WB
#define SEARCH_STATUS_DUMP_STATUS_RB SRCH_STATUS_DUMP_STATUS_RB
#define SEARCH_STATUS_DUMP_STATUS_RB_MASK SRCH_STATUS_DUMP_STATUS_RB_MASK
#define DEM_FRAME_OFF_WB DEM_FRAME_CTL_WB
#define DEM_FRAME_OFF_WB_MASK DEM_FRAME_CTL_WB_MASK
#define DEM_FRAME_OFF_WB__SET_ROLL_SYNC_MASK DEM_FRAME_CTL_WB__SET_ROLL_SYNC_MASK
#define DEM_FRAME_OFF_WB__FRAME_SYNC_BYPASS_MASK DEM_FRAME_CTL_WB__FRAME_SYNC_BYPASS_MASK
#define DEM_FRAME_OFF_WB__FRAME_OFF_MASK DEM_FRAME_CTL_WB__FRAME_OFF_MASK
#define SEARCH_POSITION_LOW_RH SRCH_POSITION_LOW_RH
#define SEARCH_POSITION_LOW_RH_MASK SRCH_POSITION_LOW_RH_MASK
#define SEARCH_POSITION_HIGH_RB SRCH_POSITION_HIGH_RB
#define SEARCH_POSITION_HIGH_RB_MASK SRCH_POSITION_HIGH_RB_MASK
#define SEARCH2_POSITION_LOW_RH SRCH2_POSITION_LOW_RH
#define SEARCH2_POSITION_LOW_RH_MASK SRCH2_POSITION_LOW_RH_MASK
#define SEARCH2_POSITION_HIGH_RB SRCH2_POSITION_HIGH_RB
#define SEARCH2_POSITION_HIGH_RB_MASK SRCH2_POSITION_HIGH_RB_MASK
#define SEARCH2_CTL_WB SRCH2_CTL_WB
#define SEARCH2_CTL_WB_MASK SRCH2_CTL_WB_MASK
#define SEARCH2_CTL_WB__SCALE_MODE_MASK SRCH2_CTL_WB__SCALE_MODE_MASK
#define SEARCH2_CTL_WB__SHOULDER_MODE_MASK SRCH2_CTL_WB__SHOULDER_MODE_MASK
#define SEARCH2_CTL_WB__ALL_ENERGIES_MASK SRCH2_CTL_WB__ALL_ENERGIES_MASK
#define SEARCH2_CTL_WB__RESET_QUEUE_PTRS_MASK SRCH2_CTL_WB__RESET_QUEUE_PTRS_MASK
#define SEARCH2_CTL_WB__RESET_RESULTS_PTRS_MASK SRCH2_CTL_WB__RESET_RESULTS_PTRS_MASK
#define SEARCH2_CTL_WB__SEARCH_ABORT_MASK SRCH2_CTL_WB__SEARCH_ABORT_MASK
#define SEARCH2_CTL_WB__STATUS_DUMP_MASK SRCH2_CTL_WB__STATUS_DUMP_MASK
#define SEARCH2_QUEUE_PTRS_RH SRCH2_QUEUE_PTRS_RH
#define SEARCH2_QUEUE_PTRS_RH_MASK SRCH2_QUEUE_PTRS_RH_MASK
#define SEARCH2_QUEUE_PTRS_RH__QUEUE_WRITE_PTR_MASK SRCH2_QUEUE_PTRS_RH__QUEUE_WRITE_PTR_MASK
#define SEARCH2_QUEUE_PTRS_RH__QUEUE_WRITE_SUB_PTR_MASK SRCH2_QUEUE_PTRS_RH__QUEUE_WRITE_SUB_PTR_MASK
#define SEARCH2_QUEUE_PTRS_RH__QUEUE_READ_PTR_MASK SRCH2_QUEUE_PTRS_RH__QUEUE_READ_PTR_MASK
#define SEARCH2_QUEUE_PTRS_RH__QUEUE_READ_SUB_PTR_MASK SRCH2_QUEUE_PTRS_RH__QUEUE_READ_SUB_PTR_MASK
#define SEARCH2_RESULTS_PTRS_RH SRCH2_RESULTS_PTRS_RH
#define SEARCH2_RESULTS_PTRS_RH_MASK SRCH2_RESULTS_PTRS_RH_MASK
#define SEARCH2_RESULTS_PTRS_RH__RESULTS_WRITE_PTR_MASK SRCH2_RESULTS_PTRS_RH__RESULTS_WRITE_PTR_MASK
#define SEARCH2_RESULTS_PTRS_RH__RESULTS_WRITE_SUB_PTR_MASK SRCH2_RESULTS_PTRS_RH__RESULTS_WRITE_SUB_PTR_MASK
#define SEARCH2_RESULTS_PTRS_RH__RESULTS_READ_PTR_MASK SRCH2_RESULTS_PTRS_RH__RESULTS_READ_PTR_MASK
#define SEARCH2_RESULTS_PTRS_RH__RESULTS_READ_SUB_PTR_MASK SRCH2_RESULTS_PTRS_RH__RESULTS_READ_SUB_PTR_MASK
#define SEARCH2_QUEUE_WH SRCH2_QUEUE_WH
#define SEARCH2_RESULTS_RH SRCH2_RESULTS_RH
#define MSM_CLK_CTL1_WH__RXCX8_MICRO_BYPASS_MASK MSM_CLK_CTL1_WH__RXCX8_BYPASS_MASK
#define MOD_PCBIT_TEST_DATA_WH PCH_PCBIT_DATA_WH
#define Fn_OTD_CFG_WB__FCH_QOF_MASK FN_OTD_CFG_WB__FCH_QOF_EN_N_MASK
#define PA_OFFSET0_WH PA_S0_OFFSET_WH
#define PA_OFFSET1_WH PA_S1_OFFSET_WH
#define PA_OFFSET2_WH PA_S2_OFFSET_WH
#define PA_OFFSET3_WH PA_S3_OFFSET_WH
#define FFE_FN_SUP_NUM_WB FN_CHAN_CTL_WB
/*===========================================================================
END INTERRUPT ALIAS
===========================================================================*/
/* Needed to access the LCD device
*/
#if defined(LT_LOUIS_DRV_DISPLAY)
#define LCD_CMD_WH (0x1000000+RAM2_BASE*256*1024) /* RAM CS2 */
#define LCD_DATA_WH (LCD_CMD_WH+0x400000) /* RS=A22 */
#endif
#endif /*MSM6000REDEFS_H*/
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