msm6000redefs.h

在高通的手机平台下,一个下载手机.bin文件到手机的flash中的工具,包含PC端的程序代码和运行在基带处理器中的代码.

#define RF_PA_R3_RISE         PA_R3_RISE_WB
#define CAGC_PA_R3_FALL       PA_R3_FALL_WB
#define RF_PA_R3_FALL         PA_R3_FALL_WB
#define CAGC_LNA_SWITCH_LB    LNA_OFFSET_LSB_WB
#define RF_LNA_SWITCH_LB      LNA_OFFSET_LSB_WB
///#define CAGC_LNA_FALL         LNA_FALL_WB
#define RF_LNA_FALL           LNA_FALL_WB
///#define CAGC_LNA_RISE         LNA_RISE_WB
#define RF_LNA_RISE           LNA_RISE_WB
#define CAGC_RAS_RAM_DATA_UB  RAS_RAM_DATA_MSB_WB
#define CAGC_RAS_RAM_DATA_LB  RAS_RAM_DATA_LSB_WB
#define RF_RAS_RAM_DATA_UB    RAS_RAM_DATA_MSB_WB
#define RF_RAS_RAM_DATA_LB    RAS_RAM_DATA_LSB_WB
#define CAGC_RAS_RAM_CNTL     AGC_RDWR_CTL_WB
#define RF_RAS_RAM_CNTL       AGC_RDWR_CTL_WB
#define CAGC_TEST_CNTL        AGC_TEST_CTL_WB
#define RF_CAGC_TEST_CNTL     AGC_TEST_CTL_WB
///#define CAGC_AGC_VALUE        AGC_VALUE_RD_RH
#define RF_CAGC_AGC_VALUE     AGC_VALUE_RD_RH
#define CAGC_TX_GAIN_CTL_UB   TX_GAIN_CTL_MSB_RB
#define RF_CAGC_TX_GAIN_CTL_UB TX_GAIN_CTL_MSB_RB
#define CAGC_TX_GAIN_CTL_LB    TX_GAIN_CTL_LSB_RB
#define RF_CAGC_TX_GAIN_CTL_LB TX_GAIN_CTL_LSB_RB
#define RF_SYNTH_STATUS_R_X    PA_ON_STATUS_RH

/*===========================================================================

                        END CAGC.H ALIAS
                        END RFG.C ALIAS

===========================================================================*/

/*  Done for MSM3100, but backward compatible with MSM3000 */

/*===========================================================================

                        START DFM.H ALIAS

===========================================================================*/

/*---------------------------------------------------------------------------
                      IQ Demodulator WRITE Registers
---------------------------------------------------------------------------*/

#define DFM_INITIAL_R           DFM_INITIAL_WH
#define DFM_DC_OFFSET_GAIN_R    DFM_DC_OFFSET_GAIN_WB
#define DFM_AGC_REF_R           DFM_AGC_REF_WB
#define DFM_AGC_ACC_MIN_R       DFM_AGC_ACC_MIN_WB
#define DFM_AGC_ACC_MAX_R       DFM_AGC_ACC_MAX_WB
#define DFM_AGC_GAIN_R          DFM_AGC_GAIN_WB
#define DFM_FREQ_LOOP_CFG_R     DFM_FREQ_LOOP_CONFIG_WB
#define DFM_PDM_CFG_R           DFM_PDM_CONFIG_WB
#define DFM_I_PDM_LSB_R         DFM_DC_PDM_0_WB
#define DFM_Q_PDM_LSB_R         DFM_DC_PDM_1_WB
#define DFM_IQ_PDM_MSB_R        DFM_DC_PDM_2_WB
#define DFM_RX_AGC_PDM_R        DFM_RXAGC_PDM_0_WB
#define DFM_FREQ_TRK_PDM_LSB_R  DFM_FREQ_PDM_0_WB
#define DFM_FREQ_TRK_PDM_MSB_R  DFM_FREQ_PDM_1_WB
#define DFM_VOC_INTF_CFG_R      DFM_VOC_INTF_CONFIG_WB
#define DFM_IQDMOD_LOOP_STAT_0_R DFM_RXIQ_STATUS_0_RB
#define DFM_IQDMOD_LOOP_STAT_1_R DFM_RX_AGC_FILTER_RB
#define DFM_IQDMOD_LOOP_STAT_2_R DFM_RX_AGC_RSSI_RB

/*---------------------------------------------------------------------------
                     TX Wideband Data WRITE Registers
---------------------------------------------------------------------------*/

#define DFM_TX_WBD_MSB_R        DFM_TXWBD_INTF_0_WB
#define DFM_TX_WBD_LSB_R        DFM_TXWBD_INTF_1_WB
#define DFM_TX_AGC_PDM_LSB_R    DFM_MAX_TX_PWR_0_WB
#define DFM_TX_AGC_PDM_MSB_R    DFM_MAX_TX_PWR_1_WB
#define DFM_FREQ_SENSE_GAIN_R   DFM_FREQ_SENS_GAIN_WB
#define DFM_TX_FM_CFG_R         DFM_TXFM_CONFIG_WB

/*---------------------------------------------------------------------------
                      TX Wideband Data READ Registers
---------------------------------------------------------------------------*/

#define DFM_TX_WBD_STAT_R       DFM_TXWBD_STATUS_RB


/*---------------------------------------------------------------------------
                      RX Wideband Data WRITE Registers
---------------------------------------------------------------------------*/

#define DFM_MIN1_0_7_R          DFM_MIN1_BYTE_0_WB        /* MIN1 bits 0..7  */
#define DFM_MIN1_8_15_R         DFM_MIN1_BYTE_1_WB        /* 8..15           */
#define DFM_MIN1_16_23_R        DFM_MIN1_BYTE_2_WB        /* 16..23          */
#define DFM_RX_WBD_BW_R         DFM_RXWBD_BANDWIDTH_WB
#define DFM_RX_WBD_CFG_R        DFM_RXWBD_CONFIG_0_WB
#define DFM_RX_WBD_WR_R         DFM_RXWBD_WR_WB

/*---------------------------------------------------------------------------
                     RX Wideband Data READ Registers
---------------------------------------------------------------------------*/

#define DFM_RX_WBD_0_7_R        DFM_RXWBD_STAT_0_RB
#define DFM_RX_WBD_8_15_R       DFM_RXWBD_STAT_1_RB
#define DFM_RX_WBD_16_23_R      DFM_RXWBD_STAT_2_RB
#define DFM_RX_WBD_24_27_R      DFM_RXWBD_STAT_3_RB
#define DFM_RX_WBD_RD_R         DFM_RXWBD_RD_RB
#define DFM_WORD_SYNC_COUNT_R   DFM_WORD_SYNC_COUNT_RB

/*===========================================================================

                        END DFM.H ALIAS

===========================================================================*/


/*===========================================================================

                        START SNDRING.H ALIAS

===========================================================================*/

#define SND_RINGER_A          RINGER_MN_A_DUTY_LSB_WB
#define SND_RINGER_B          RINGER_MN_B_DUTY_LSB_WB

/*===========================================================================

                        END SNDRING.H ALIAS

===========================================================================*/


/*===========================================================================

                        START CLKM2P.C AND CLKARM.C ALIAS

===========================================================================*/

#define CLK_TICK_CTL          TIME_TICK_CTL_WB
#define CLK_TICK_CNT          TIME_TICK_INT_MSB_RB

/*===========================================================================

                        END CLKM2P.C AND CLKARM.C ALIAS

===========================================================================*/


/*===========================================================================

                        START VOC_CORE.H

===========================================================================*/

#define VC_RESET                 VOC_RESET_WB
#define VC_ENC_FRAME_ADVANCE     ENC_FRAME_ADVANCE_WB
#define VC_DEC_FRAME_ADVANCE     DEC_FRAME_ADVANCE_WB
#define VC_DEC_INT_ADVANCE       DEC_INT_ADVANCE_WB

#define VC_TX_PCM_CONTROL        TX_PCM_CONTROL_WB
#define VC_RX_PCM_CONTROL        RX_PCM_CONTROL_WB

#define VC_DEC_PCM_WR_MSB        DEC_PCM_WR_MSB_WB
#define VC_DEC_PCM_WR_LSB        DEC_PCM_WR_LSB_WB

#define VC_TEST_CONTROL_1        TEST_CONTROL_1_WB
#define VC_TEST_CONTROL_2        MSM_CLK_CTL5_WB

#define VC_MODE_CONTROL          MODE_CONTROL_WB
#define VC_VOX_CONTROL           VOX_CONTROL_WB
#define VC_PEEK_POKE_CONTROL     PEEK_POKE_CONTROL_WB

#define VC_ENC_SAMP_CNT          VOC_ENC_SAMP_CNT_RB
#define VC_POKE_ADDR_LSB         PEEK_POKE_ADDR_LSB_WB

#define VC_DEC_SAMP_CNT          VOC_DEC_SAMP_CNT_RB
#define VC_POKE_DATA_MSB         POKE_DATA_MSB_WB
#define VC_POKE_DATA_LSB         POKE_DATA_LSB_WB

#define VC_ENC_RATE_CONTROL      ENC_RATE_CONTROL_WB
#define VC_ENC_RATE_LIMIT_FACTOR ENC_RATE_LIMIT_FACTOR_WB
#define VC_FM_AUDIO_CONFIG       FM_AUDIO_CONFIG_WB

/* Alias VOX Parameter Registers (for qdsp1) as AGC control for qdsp1+. */
#define VC_ENERGY_DECAY_MSB      ENERGY_DECAY_FAC_MSB_WB
#define VC_ENERGY_DECAY_LSB      ENERGY_DECAY_FAC_LSB_WB
#define VC_BG_NOISE_DECAY_MSB    BGN_DECAY_FAC_MSB_WB
#define VC_BG_NOISE_DECAY_LSB    BGN_DECAY_FAC_LSB_WB
#define VC_FWD_AGC_MSB           ENERGY_DECAY_FAC_MSB_WB
#define VC_FWD_AGC_LSB           ENERGY_DECAY_FAC_LSB_WB
#define VC_REV_AGC_MSB           BGN_DECAY_FAC_MSB_WB
#define VC_REV_AGC_LSB           BGN_DECAY_FAC_LSB_WB

#define VC_FM_TEST_CONTROL       FM_TEST_CTL_WB

#define VC_SAT_ECC               VOC_FM_CONFIG_WB
#define VC_SAT_LEVEL             SAT_LEVEL_WB
#define VC_SAT_THRESHOLD         SAT_THRESHOLD_WB

/* Alias Dec Voc Thresh MSB Register (qdsp1) as NS Control for qdsp1+. */
#define VC_NS_CONTROL            DEC_VOX_THRESHOLD_MSB_WB
#define VC_DEC_VOX_THRESH_MSB    DEC_VOX_THRESHOLD_MSB_WB

#define VC_DEC_VOX_THRESH_LSB    DEC_VOX_THRESHOLD_LSB_WB

#define VC_TX_DEVIATION_LIMIT    TX_DEVIATION_LIMIT_WB
#define VC_FM_TX_GAIN            FM_TX_GAIN_WB

/* Alias Enc Weighting MSB Registers (qdsp1) as VR Control for qdsp1+. */
#define VC_VR_CONTROL_MSB        ENC_WEIGHTING_FAC_MSB_WB
#define VC_VR_CONTROL_LSB        ENC_WEIGHTING_FAC_LSB_WB
#define VC_ENC_WEIGHTING_MSB     ENC_WEIGHTING_FAC_MSB_WB
#define VC_ENC_WEIGHTING_LSB     ENC_WEIGHTING_FAC_LSB_WB

#define VC_FM_RX_GAIN            FM_RX_GAIN_WB

#define VC_BG_NOISE_FLOOR_MSB    DEC_BGN_FLOOR_MSB_WB
#define VC_BG_NOISE_FLOOR_LSB    DEC_BGN_FLOOR_LSB_WB

#define VC_DTMF_DURATION_MSB     DTMF_DURATION_MSB_WB
#define VC_DTMF_DURATION_LSB     DTMF_DURATION_LSB_WB

#define VC_DTMF_HIGH_MSB         DTMF_HIGH_MSB_WB
#define VC_DTMF_HIGH_LSB         DTMF_HIGH_LSB_WB

#define VC_DTMF_LOW_MSB          DTMF_LOW_MSB_WB
#define VC_DTMF_LOW_LSB          DTMF_LOW_LSB_WB

#define VC_DTMF_VOL_MSB          DTMF_VOLUME_MSB_WB
#define VC_DTMF_VOL_LSB          DTMF_VOLUME_LSB_WB

#define VC_FM_DTMF_RX_GAIN       DTMF_FM_RX_GAIN_WB
#define VC_FM_DTMF_TX_GAIN       DTMF_FM_TX_GAIN_WB

#define VC_DEC_VOLUME_MSB        DEC_VOLUME_MSB_WB
#define VC_DEC_VOLUME_LSB        DEC_VOLUME_LSB_WB

#define VC_PCM_PAD_CONTROL       PCM_PAD_CONTROL_WB

#define VC_PCM_CONTROL_WORD_MSB  PCM_CONTROL_WORD_MSB_WB
#define VC_PCM_CONTROL_WORD_LSB  PCM_CONTROL_WORD_LSB_WB

#define VC_IO_CONTROL            IO_CONTROL_WB

#define VC_CLEAR_ENC_INT         CLEAR_ENC_INT_WB
#define VC_CLEAR_DEC_INT         CLEAR_DEC_INT_WB

#define VC_DEC_PACKET            DEC_PACKET_WB

#define CODEC_CTL                CODEC_CTL_WH

#define VC_ENC_PCM_RD_MSB        ENC_PCM_RD_MSB_RB
#define VC_ENC_PCM_RD_LSB        ENC_PCM_RD_LSB_RB

#define VC_ENC_PCM_WR_MSB        ENC_PCM_WR_MSB_WB
#define VC_ENC_PCM_WR_LSB        ENC_PCM_WR_LSB_WB

#define VC_STATUS                VOC_STATUS_RB
#define VC_HW_VERSION            HW_REVISION_NUMBER_RH

#define VC_FM_STATUS             FM_STATUS_RB
#define VC_ENC_PACKET            ENC_PACKET_RB

/*===========================================================================

                        END VOC_CORE.H

===========================================================================*/


/*===========================================================================

                        START DECI.H

===========================================================================*/

#define DEC_MODE           DECMODE_WB
#define DEC_SMTDATA        SMTDATA_WB
#define DEC_OBADDR         OBADDRESS_WB

#define DEC_Q2448          QT8_QT4_WB
#define DEC_Q96192         QT2_QT1_WB


#define DEC_TESTCON        DEC_TESTCON_WB
#define DEC_TESTMUX        DEC_TESTSEL_WB
#define DEC_TEST_RAM_SEL   TEST_MEM_SEL_WH
#define DEC_TEST_POINT_SEL TEST_POINT_SEL_WH
#define DEC_SYNC           DEC_TESTSYNC_WB
#define DEC_CRC            DEC_CRC_WH
#define DEC_RESET          DEC_RESET_WB

#define DEC_CLK_CTL_1     MSM_CLK_CTL1_WH
#define DEC_CLK_CTL_2     MSM_CLK_CTL2_WH
#define DEC_CLK_CTL_3     MSM_CLK_CTL3_WH
#define DEC_CLK_CTL_4     MSM_CLK_CTL4_WH

#define DEC_DATA          DECDATA_RH
#define DEC_STATUS        DECSTATUS_RB

#define DEC_SER8          SER8_RB
#define DEC_SER4          SER4_RB
#define DEC_SER2          SER2_RB
#define DEC_SER1          SER1_RB

#define DEC_TESTOUT       DEC_TESTOUT_RH


/*===========================================================================