📄 msm6000redefs.h
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#ifndef MSM6000REDEFS_H
#define MSM6000REDEFS_H
/*===========================================================================
MSM6000 REGISTER REDEFINITION HEADER FILE
DESCRIPTION
This file contains MSM6000 register redefinitions.
Copyright (c) 1998-2002 by QUALCOMM, Incorporated. All Rights Reserved.
===========================================================================*/
/*===========================================================================
EDIT HISTORY FOR FILE
This section contains comments describing changes made to this file.
Notice that changes are listed in reverse chronological order.
$Header: L:/src/asw/MSM6000/vcs/msm6000redefs.h_v 1.4 12 Aug 2002 19:32:50 cryan $
when who what, where, why
-------- --- ----------------------------------------------------------
01/17/05 nony.wu Added LCD port define
-------- --- ----------------------------------------------------------
03/20/02 hjr Deleted unused register definitions.
02/07/02 bgc Undefined MSM3_DUMMY so that use of it will syntax error.
The address address 03001000 aliases to DMOD_RESET.
03/12/01 djd Updated DMOD_R_FRSSI.
11/27/00 rmd Updated AGC_CTL3_WB mask definitions
11/09/00 rmd Added PS_HOLD register redefinitions from msmXXXXbits.h
10/23/00 rmd Initial Revision
===========================================================================*/
/*===========================================================================
START DMOD.H ALIAS
===========================================================================*/
/*---------------------------------------------------------------------------
Write Registers
---------------------------------------------------------------------------*/
#define DMOD_RESET DEMOD_RESET_WB
#define DMOD_W_SRCH_CTL SRCH_CTL_WB
#define DMOD_ETE_0 SRCH_TH_ENERGY_LOW_WB /* Bits 7:0 */
#define DMOD_ETE_1 SRCH_TH_ENERGY_HIGH_WB /* Bits 15:8 */
#define DMOD_SIT SRCH_INTG_TIME_WB /* Bits 7:0 */
#define DMOD_ETT SRCH_TH_TIME_WB /* Bits 7:0 */
#define DMOD_SBO_0 SRCH_OFFSET_LOW_WB /* Bits 7:0 */
#define DMOD_SBO_1 SRCH_OFFSET_HIGH_WB /* Bits 14:8 */
#define DMOD_SPNIM_0 SRCH_MASK_I_LOW_WB /* Bits 7:0 */
#define DMOD_SPNIM_1 SRCH_MASK_I_HIGH_WB /* Bits 14:8 */
#define DMOD_SPNQM_0 SRCH_MASK_Q_LOW_WB /* Bits 7:0 */
#define DMOD_SPNQM_1 SRCH_MASK_Q_HIGH_WB /* Bits 14:0 */
#define DMOD_SS_0 SRCH_SLEW_LOW_WB /* Bits 7:0 */
#define DMOD_SS_1 SRCH_SLEW_MID_WB /* Bits 15:0 */
#define DMOD_SS_2 SRCH_SLEW_HIGH_WB /* Bits 17:16 */
#define DMOD_SAP SRCH_ACC_PASS_WB
#define DMOD_SN_0 SRCH_NUM_LOW_WB
#define DMOD_SN_1 SRCH_NUM_HIGH_WB /* MSM23 Only */
#define DMOD_PC_F0_CELL_EN FFE_POWER_CTL_F0_CELLN_EN_WB
#define DMOD_PC_F1_CELL_EN FFE_POWER_CTL_F1_CELLN_EN_WB
#define DMOD_PC_F2_CELL_EN FFE_POWER_CTL_F2_CELLN_EN_WB
#define DMOD_PC_F3_CELL_EN FFE_POWER_CTL_F3_CELLN_EN_WB
#define DMOD_W_PCPD TX_GAIN_ADJ_WR_WB
#define DMOD_PCC POWER_COMB_CTL_WB
#define DMOD_TT_K1_GAIN FFE_TT_K1_GAIN_WB /* K1 Gain Register */
#define DMOD_TT_K2_GAIN FFE_TT_K2_GAIN_WB /* K2 Gain Register */
#define DMOD_F_CTL_2 FFE_FINGER_CTL2_WB
#define DMOD_W_TTA_0 FFE_TT_ACCUM_LOWER_WB /* Bits 7:0 */
#define DMOD_W_TTA_1 FFE_TT_ACCUM_UPPER_WB /* Bits 15:8 */
#define DMOD_W_FRSSI FFE_FN_RSSI_INIT_WB
#define DMOD_OFFSET_0 FFE_FN_BINARY_OFFSET_LOWER_WB /* Bits 7:0 */
#define DMOD_OFFSET_1 FFE_FN_BINARY_OFFSET_UPPER_WB /* Bits 14:8 */
#define DMOD_IMASK_0 FFE_FN_PN_I_MASK_LOWER_WB /* Bits 7:0 */
#define DMOD_IMASK_1 FFE_FN_PN_I_MASK_UPPER_WB /* Bits 14:8 */
#define DMOD_QMASK_0 FFE_FN_PN_Q_MASK_LOWER_WB /* Bits 7:0 */
#define DMOD_QMASK_1 FFE_FN_PN_Q_MASK_UPPER_WB /* Bits 14:0 */
#define DMOD_WALSH FFE_FN_CODE_CHAN_ID_WB
#define DMOD_SLEW_0 FFE_SLEW_VALUE_LOWER_WB /* Bits 7:0 */
#define DMOD_SLEW_1 FFE_SLEW_VALUE_MID_WB /* Bits 15:8 */
#define DMOD_SLEW_2 FFE_SLEW_VALUE_UPPER_WB /* Bits 18:16 */
#define DMOD_F_CTL_1 FFE_FINGER_CTL1_WB
#define DMOD_PILOT_GAIN FFE_PILOT_FILT_GAIN_WB
#define DMOD_F_PWR_THRESH FFE_FN_PWR_THRESH_WB
#define DMOD_F_LOCK_LO FFE_LOCK_THRESH_LOWER_WB /* Not a paged reg in MSM23 */
#define DMOD_F_LOCK_UP FFE_LOCK_THRESH_UPPER_WB /* Not a paged reg in MSM23 */
#define DMOD_FREQ_COMB_GAIN FREQ_COMB_GAIN_WB
#define DMOD_FREQ_COMB_CTL FREQ_COMB_CTL_WB
#define DMOD_CAR_FREQ_0 CARRIER_FREQ_ERR_WR_LSB_WB /* Bits 7:0 */
#define DMOD_CAR_FREQ_1 CARRIER_FREQ_ERR_WR_MSB_WB /* Bits 15:8 */
#define DMOD_W_SC_CTL_0 SYMB_COMB_CTL0_WB
#define DMOD_SC_CTL_1 SYMB_COMB_CTL1_WH
#define DMOD_POS_LATCH SYMB_COMB_POS_DUMP_WB
#define DMOD_FREQ_ADJ_0 SYMB_COMB_FREQ_ADJ_LOWER_WB /* Bits 7:0 */
#define DMOD_FREQ_ADJ_1 SYMB_COMB_FREQ_ADJ_UPPER_WB /* Bits 15:8 */
#define DMOD_W_I_PDM I_OFFSET_WR_WB
#define DMOD_W_Q_PDM Q_OFFSET_WR_WB
#define DMOD_AGC_CTL IQ_OFFSET_CTL_WB
#define DMOD_LONG_0 SYMB_COMB_LONG_CODE_LD_0_WB /* Bits 7:0 */
#define DMOD_LONG_1 SYMB_COMB_LONG_CODE_LD_1_WB /* Bits 15:8 */
#define DMOD_LONG_2 SYMB_COMB_LONG_CODE_LD_2_WB /* Bits 23:16 */
#define DMOD_LONG_3 SYMB_COMB_LONG_CODE_LD_3_WB /* Bits 31:24 */
#define DMOD_LONG_4 SYMB_COMB_LONG_CODE_LD_4_WB /* Bits 39:32 */
#define DMOD_LONG_5 SYMB_COMB_LONG_CODE_LD_5_WB /* Bits 41:40 */
#define DMOD_LONG_MASK_0 SYMB_COMB_LONG_CODE_MASK_0_WB /* Bits 7:0 */
#define DMOD_LONG_MASK_1 SYMB_COMB_LONG_CODE_MASK_1_WB /* Bits 15:8 */
#define DMOD_LONG_MASK_2 SYMB_COMB_LONG_CODE_MASK_2_WB /* Bits 23:16 */
#define DMOD_LONG_MASK_3 SYMB_COMB_LONG_CODE_MASK_3_WB /* Bits 31:24 */
#define DMOD_LONG_MASK_4 SYMB_COMB_LONG_CODE_MASK_4_WB /* Bits 39:32 */
#define DMOD_LONG_MASK_5 SYMB_COMB_LONG_CODE_MASK_5_WB /* Bits 41:40 */
#define DMOD_PDM2 PDM2_CTL_WB
#define DMOD_PA_VGG_CTL PDM2_CTL_WB
#define DMOD_PDM1 PDM1_CTL_WB
#define DMOD_TX_GAIN_COMP PDM1_CTL_WB
#define DMOD_TCXO_BLK_TSEN TCXO_PDM_CTL_WB
#define DMOD_EPOCH EPOCH_WR_WB
#define DMOD_F_PAGE FFE_FINGER_PAGE_REG_WB
#define DMOD_SLEEP_CTL SLEEP_CTL_WB
#define DMOD_SLEEP_TIME_0 POWER_DOWN_SLEEP_INTERVAL_0_WH /* Bits 7:0 */
#define DMOD_SLEEP_TIME_1 POWER_DOWN_SLEEP_INTERVAL_0_WH /* Bits 15:8 */
#define DMOD_SLEEP_TIME_2 POWER_DOWN_SLEEP_INTERVAL_1_WH /* Bits 23:16 */
#define DMOD_SLEEP_TIME_3 POWER_DOWN_SLEEP_INTERVAL_1_WH /* Bits 31:24 */
#define DMOD_WARM_TIME_0 POWER_DOWN_WU_TIME_WH /* Bits 7:0 */
#define DMOD_WARM_TIME_1 POWER_DOWN_WU_TIME_WH /* Bits 15:8 */
#define DMOD_FM_CLK_MDIV_0 YAMN1_CLK_MDIV_LSB_WB
#define DMOD_FM_CLK_MDIV_1 YAMN1_CLK_MDIV_MSB_WB /* MSM23 Only */
#define DMOD_FM_CLK_NDIV_0 YAMN1_CLK_NDIV_LSB_WB
#define DMOD_FM_CLK_NDIV_1 YAMN1_CLK_NDIV_MSB_WB /* MSM23 Only */
#define DMOD_FM_CLK_DUTY_0 YAMN1_CLK_DUTY_LSB_WB
#define DMOD_FM_CLK_DUTY_1 YAMN1_CLK_DUTY_MSB_WB /* MSM23 Only */
//----------------------------------------------------------------------------
// PS_HOLD BIT
// There is a register which contains the control for the GPIO bit which
// sets the hold for the voltage regulators to keep the phone from being
// powered-off. During boot, the other bits in the register can be left
// as inputs.
//----------------------------------------------------------------------------
#define PS_HOLD_GPIO_R GPIO_INT_OUT_1_WH //GPIO output register
#define PS_HELD_GPIO_R GPIO_INT_IN_1_WH //GPIO input register
#define PS_HOLD_TSEN_R GPIO_INT_TSEN_1_WH //GPIO tri-state enable register
/*---------------------------------------------------------------------------
Read Registers
---------------------------------------------------------------------------*/
#define DMOD_R_SRCH_CTL SRCH_DMA_ERROR_RB
#define DMOD_SP_0 SRCH_POSITION_LOW_RB /* Bits 7:0 */
#define DMOD_SP_1 SRCH_POSITION_MID_RB /* Bits 15:8 */
#define DMOD_SP_2 SRCH_POSITION_HIGH_RB /* Bits 17:16 */
#define DMOD_DMA_0 SRCH_DMA_DATA_RB
#define DMOD_SRCH_MAX_ENG_0 SRCH_MAX_ENERGY_LOW_RB /* Bits 7:0 */
#define DMOD_SRCH_MAX_ENG_1 SRCH_MAX_ENERGY_HIGH_RB /* Bits 15:8 */
#define DMOD_SRCH_MAX_SEL SRCH_MAX_SELECT_WB /* Bits 1:0 */
#define DMOD_SRCH_MAX_INX_0 SRCH_MAX_INDEX_LOW_RB /* Bits 7:0 */
#define DMOD_SRCH_MAX_INX_1 SRCH_MAX_INDEX_HIGH_RB /* Bits 10:8 */
#define DMOD_R_PCPD TX_GAIN_ADJ_RD_RH
#define DMOD_LOCK_RSSI_GAIN FFE_RSSI_FILT_GAIN_WB /* Bits 7:0 */
#define DMOD_R_FRSSI FN_LOCK_RSSI_RH /* Bits 15:0 */
#define DMOD_POS_0 FN_POSITION_LOWER_RB /* Bits 7:0 */
#define DMOD_POS_1 FN_POSITION_MID_RB /* Bits 15:8 */
#define DMOD_POS_2 FN_POSITION_UPPER_RB /* Bits 17:16 */
#define DMOD_FREQ_SET_0 CARRIER_FREQ_ERR_RD_LSB_RB /* Bits 7:0 */
#define DMOD_FREQ_SET_1 CARRIER_FREQ_ERR_RD_MSB_RB /* Bits 15:8 */
#define DMOD_R_SC_CTL_0 SYMB_COMB_STATUS0_RB
#define DMOD_POS_PW_0 SYMB_COMB_POSITION2_LOWER_RB /* Bits 7:0 */
#define DMOD_POS_PW_1 SYMB_COMB_POSITION2_UPPER_RB /* Bits 15:8 */
#define DMOD_R_I_PDM I_OFFSET_RD_RB
#define DMOD_R_Q_PDM Q_OFFSET_RD_RB
#define DMOD_R_LONG_0 SYMB_COMB_LONG_CODE_RD_0_RB /* Bits 7:0 */
#define DMOD_R_LONG_1 SYMB_COMB_LONG_CODE_RD_1_RB /* Bits 15:8 */
#define DMOD_R_LONG_2 SYMB_COMB_LONG_CODE_RD_2_RB /* Bits 23:16 */
#define DMOD_R_LONG_3 SYMB_COMB_LONG_CODE_RD_3_RB /* Bits 31:24 */
#define DMOD_R_LONG_4 SYMB_COMB_LONG_CODE_RD_4_RB /* Bits 39:32 */
#define DMOD_R_LONG_5 SYMB_COMB_LONG_CODE_RD_5_RB /* Bits 41:40 */
#define DMOD_INT_STATUS_0 INT_STATUS_0_RH
#define DMOD_INT_STATUS_1 INT_STATUS_1_RH
#define DMOD_KEY_READ_IN KEYSENSE_RD_RB
/*===========================================================================
START ENCI.H ALIAS
===========================================================================*/
/*---------------------------------------------------------------------------
Write Registers
---------------------------------------------------------------------------*/
#define ENC_I_PN_S0 I_PN_STATE_0_WB /* bits 7:0 */
#define ENC_I_PN_S1 I_PN_STATE_1_WB /* bits 14:8 */
#define ENC_Q_PN_S0 Q_PN_STATE_0_WB /* bits 7:0 */
#define ENC_Q_PN_S1 Q_PN_STATE_1_WB /* bits 14:8 */
#define ENC_U_PN_S0 U_PN_STATE_0_WB /* bits 7:0 */
#define ENC_U_PN_S1 U_PN_STATE_1_WB /* bits 15:8 */
#define ENC_U_PN_S2 U_PN_STATE_2_WB /* bits 23:16 */
#define ENC_U_PN_S3 U_PN_STATE_3_WB /* bits 31:24 */
#define ENC_U_PN_S4 U_PN_STATE_4_WB /* bits 39:32 */
#define ENC_U_PN_S5 U_PN_STATE_5_WB /* bits 41:40 and bozo bit */
#define ENC_U_PN_M0 U_PN_MASK_0_WB /* bits 7:0 */
#define ENC_U_PN_M1 U_PN_MASK_1_WB /* bits 15:8 */
#define ENC_U_PN_M2 U_PN_MASK_2_WB /* bits 23:16 */
#define ENC_U_PN_M3 U_PN_MASK_3_WB /* bits 31:24 */
#define ENC_U_PN_M4 U_PN_MASK_4_WB /* bits 39:32 */
#define ENC_U_PN_M5 U_PN_MASK_5_WB /* bits 41:40 */
#define ENC_PA_WARMUP PA_WARMUP_WB
#define ENC_WSYM_STATE WSYM_STATE_WB
#define ENC_TXSYNC_ST_0 TXSYNC_ST_0_WB /* Bits 7:0 */
#define ENC_TXSYNC_ST_1 TXSYNC_ST_1_WB /* Bits 13:8 */
#define ENC_SYSFR_STATE SYSFR_STATE_WB /* Bits 5:0 */
#define ENC_INT_ST ENC_INT_ST_WB
#define ENC_DATA_WR ENC_DATA_WB
#define ENC_CTL ENC_CTL_WB /* Encoder Control */
#define ENC_CLK_CTL MOD_CLK_CTL_WH /* Clock Control */
#define ENC_MISC_CTL MOD_MISC_CTL_WB /* Miscellanious control */
#define ENC_FRAME_OFF FRAME_OFF_WB
#define ENC_TX_TST TX_DATA_TEST_WB
#define ENC_TST_CTL MOD_TEST_CTL_WH
#define ENC_CRC_UB CRC_MSB_WB /* CRC Polynomial Upper Bits */
#define ENC_CRC_LB CRC_LSB_WB /* CRC Polynomial Lower Bits */
#define ENC_TEST_POINT_SEL TEST_POINT_SEL_WH
/*---------------------------------------------------------------------------
Address-Activated Registers
---------------------------------------------------------------------------*/
#define ENC_RESET MOD_RESET_WB /* Reset the chip state. */
#define ENC_I_CLK TX_I_CLK_WB /* Pulse TX_I_SCLK in test mode */
/*---------------------------------------------------------------------------
Read Registers
---------------------------------------------------------------------------*/
#define ENC_MASK_DATA MASK_DATA_RB /* MASK_DATA from DBR */
#define ENC_STATUS MOD_STATUS_RB
#define MOD_SCH_ENC_DATA_WH SCH_ENC_DATA_WH
/*===========================================================================
END ENCI.H ALIAS
===========================================================================*/
/*===========================================================================
START CAGC.H ALIAS
START RFMSM.C ALIAS
===========================================================================*/
#define CAGC_CNTL AGC_CTL_WB
#define RF_CAGC_CNTL AGC_CTL_WB
#define CAGC_OUT_CTL AGC_CTL2_WB
#define RF_CAGC_OUT_CTL AGC_CTL2_WB
#define CAGC_DATA_1 RX_AGC_ADJ_WR_WB
#define RF_CAGC_DATA_1 RX_AGC_ADJ_WR_WB
#define CAGC_DATA_2 TX_AGC_ADJ_WR_MSB_WB
#define RF_CAGC_DATA_2 TX_AGC_ADJ_WR_MSB_WB
#define CAGC_DATA_3 AGC_CTL3_WB
#define RF_CAGC_DATA_3 AGC_CTL3_WB
/* This register is [0:5] bits long but we are redefining it as a WH to keep
the definition consistent with the other MSMs */
#define AGC_CTL3_WH AGC_CTL3_WB
#define CAGC_DATA_4 AGC_CTL4_WB
#define RF_CAGC_DATA_4 AGC_CTL4_WB
#define CAGC_CTL_5 AGC_CTL5_WB
#define RF_CAGC_CTL_5 AGC_CTL5_WB
#define CAGC_CTL_6 AGC_CTL6_WB
#define RF_CAGC_CTL_6 AGC_CTL6_WB
#define CAGC_AGC_VALUE_MAX AGC_VALUE_MAX_WB
#define RF_AGC_VALUE_MAX AGC_VALUE_MAX_WB
///#define CAGC_AGC_VALUE_MIN AGC_VALUE_MIN_WB
#define RF_AGC_VALUE_MIN AGC_VALUE_MIN_WB
#define CAGC_IM_STATE_CTL IM_STATE_CTL_WB
#define RF_IM_STATE_CTL IM_STATE_CTL_WB
#define CAGC_PWR_LIM_LB TX_GAIN_LIMIT_LSB_WB
#define RF_CAGC_PWR_LIM_LB TX_GAIN_LIMIT_LSB_WB
#define CAGC_PA_R1_RISE PA_R1_RISE_WB
#define RF_PA_R1_RISE PA_R1_RISE_WB
#define CAGC_PA_R1_FALL PA_R1_FALL_WB
#define RF_PA_R1_FALL PA_R1_FALL_WB
#define CAGC_PA_R2_RISE PA_R2_RISE_WB
#define RF_PA_R2_RISE PA_R2_RISE_WB
#define CAGC_PA_R2_FALL PA_R2_FALL_WB
#define RF_PA_R2_FALL PA_R2_FALL_WB
#define CAGC_PA_R3_RISE PA_R3_RISE_WB
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