dloaduart.h

在高通的手机平台下,一个下载手机.bin文件到手机的flash中的工具,包含PC端的程序代码和运行在基带处理器中的代码.

#include "comdef.h"
#include "msm6000reg.h"
#include "msm6000bits.h"
#include "msm6000redefs.h"
#include "clkrgm_6000.h"


#define  UART_CSR_1152K_BPS 0xff            /* 115,200 bps                   */


#define  UART_CSR_384K_BPS 0xdd           /* 38,400 bps                    */
                /* This is really only 57.6 kbps with the clock workaround */

typedef enum
{
 UART_1152K_BPS,
 UART_2304K_BPS,
 UART_4608K_BPS
} baud_rate_type;



  /* ARM based targets use memory mapped i/o, so the inp/outp calls are
  ** macroized to access memory directly
  */
  #define inp(port)         (*((volatile byte *) (port)))
  #define inpw(port)        (*((volatile word *) (port)))
  #define inpdw(port)       (*((volatile dword *)(port)))
  
  #define outp(port, val)   (*((volatile byte *) (port)) = ((byte) (val)))
  #define outpw(port, val)  (*((volatile word *) (port)) = ((word) (val)))
  #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
  
  

#define BOOTHW_KICK_WATCHDOG() \
      outp(SLEEP_CTL_WB, SLEEP_CTL_WB__WATCH_DOG_MASK); \
      outp(SLEEP_CTL_WB, 0)    




#define MSM_BASE          CHIP_BASE             /* Base MSM Memory Mapped address */

#define MSM_INX( io ) (((io) - MSM_BASE)/4)



#define MSM_OUTHM_NO_INTLOCK( io, mask, val) \
  MSM_image_H[MSM_INX(io)] = (MSM_image_H[ MSM_INX( io ) ] & (word)(~(mask))) | \
         ((word)((val) & (mask)));\
  (void) outpw( io, ((word)MSM_image_H[ MSM_INX( io ) ]));\


#define MSM_OUTHM( io, mask, val) \
  MSM_OUTHM_NO_INTLOCK( io, mask, val);




#define MSM_END           (GPIO_INT_CTL_3_WH + 4)   
                                                /* End MSM Memory Mapped address */
                                                /* Add 4 for MSM3_DUMMY location */

#define MSM_MAX_INX       (((MSM_END - CHIP_BASE)/4) + 1)




#ifndef DLOADUART_H
#define DLOADUART_H

/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*

                   U A R T   D R I V E R  H E A D E R 

 GENERAL DESCRIPTION
  This header file contains the definitions of the MSM2.x UART 
  hardware registers needed for the boot downloader.

  Copyright (c) 1995,1996,1997,1998,1999 by QUALCOMM Incorporated.
  Copyright (c) 2000                     by QUALCOMM Incorporated.
  All Rights Reserved.
*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/


/*===========================================================================

                           EDIT HISTORY FOR FILE
  This section contains comments describing changes made to the module.
  Notice that changes are listed in reverse chronological order.

$Header:   L:/src/asw/MSM5105/vcs/dloaduart.h_v   1.4   04 Dec 2000 22:11:06   ddalke  $
   
when       who     what, where, why
--------   ---     ----------------------------------------------------------
11/01/00   rmd     Replaced FEATURE_TXCO19XX (XX = 2, 8, 68) with 
                   (BSP_OSCILLATOR_IN == BSP_TCXO_19PXX_MHZ).
10/25/00   rmd     Moved bit definitions to msm5XXXbits.h.
08/31/00   jcw     Merge of MSM5000 and MSM3300 versions
06/28/00   aks     UART clock values added for TCXO1920 and TCXO1980.
06/05/00   jc      Added support for FEATURE_TCXO1920
08/05/98   hcg     created, taken from flashprg

===========================================================================*/

/* <EJECT> */
/*===========================================================================

                     INCLUDE FILES FOR MODULE

===========================================================================*/
//#include "bsp.h"

/*===========================================================================

            LOCAL DEFINITIONS AND DECLARATIONS FOR MODULE

This section contains local definitions for constants, macros, types,
variables and other items needed by this module.

===========================================================================*/



/* For M/N counter registers */

/* ----------------------------------------------------------------------- */
/* Setup the M/N:D counters based on TCXO                                  */
/* ----------------------------------------------------------------------- */
#if (BSP_OSCILLATOR_IN == BSP_TCXO_19P2_MHZ) /* TCXO = 19.20 */

#ifdef UART_HALF_BAUD
  #define M_VAL  (unsigned)192     /* M value (9 bits) */
#else
  #define M_VAL  (unsigned)384     /* M value (9 bits) */
#endif  
  #define N_VAL  (unsigned)1000    /* N value (11 bits) */
  #define D_VAL  (unsigned)500     /* D value - half of N_VAL (10 bits) */
    
#elif (BSP_OSCILLATOR_IN == BSP_TCXO_19P8_MHZ) /* TCXO = 19.80 */ 
  
  /* Note: These M/N:D values produce 4 hz of error in the 
  **       generation of the 1.8432 Mhz UART clock.  This is
  **       neglible. 
  */
#ifdef UART_HALF_BAUD
  #define M_VAL  (unsigned)177     /* M value (9 bits) */
#else
  #define M_VAL  (unsigned)353     /* M value (9 bits) */
#endif  
  #define N_VAL  (unsigned)948     /* N value (11 bits) */
  #define D_VAL  (unsigned)474     /* D value - half of N_VAL (10 bits) */

#else /*(BSP_OSCILLATOR_IN == BSP_TCXO_19P68_MHZ)*/   /* TCXO = 19.68 */ 
 
#ifdef UART_HALF_BAUD
  #define M_VAL  (unsigned)192     /* M value (9 bits) */
#else
  #define M_VAL  (unsigned)384     /* M value (9 bits) */
#endif  
  #define N_VAL  (unsigned)1025    /* N value (11 bits) */
  #define D_VAL  (unsigned)513     /* D value - half of N_VAL (10 bits) */
    
#endif

#define N_MINUS_M_VAL (unsigned)((0x7ff - (N_VAL - M_VAL)))    /* '(N-M) */


/* ----------------------------------------------------------------------- */
/* Calculate the proper M, N, D, and MND register values                   */
/* ----------------------------------------------------------------------- */
#define M_REG_VAL   (byte) ( (M_VAL & 0x1fe)>>1 )           /* MS 8/9 bits  */
#define N_REG_VAL   (byte) ( (N_MINUS_M_VAL & 0x7f8) >> 3 ) /* MS 8/11 bits */
#define D_REG_VAL   (byte) ( (D_VAL & 0x3fc) >> 2 )         /* MS 8/10 bits */
#define MND_REG_VAL (byte) ( ((M_VAL & 0x01) << 5) |          \
                                    ((N_MINUS_M_VAL & 0x07 ) << 2) | \
                                     (D_VAL & 0x3) )
                     /* LS 1 bit of M, LS 3 bits of N, and LS 2 bits of D */

/* Error return code from uart_receive_byte */
/* This int value must not be any valid unsigned char value. */
#define  UART_RX_ERR    (-1)
#define  UART_TIMEOUT   (-2)

#define  TIMEOUT_ENABLED   TRUE
#define  TIMEOUT_DISABLED  FALSE

/*-   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -*/

//#define  UART_CSR_384K_BPS 0xdd           /* 38,400 bps                    */
                /* This is really only 19.2 kbps with the clock workaround */
//#define  UART_CSR_1152K_BPS 0xff          /* 115,200 bps                   */
                /* This is really only 57.6 kbps with the clock workaround */

#define  UART_MVR_V        M_REG_VAL

#define  UART_NVR_V        N_REG_VAL

#define  UART_DVR_V        D_REG_VAL

#define  UART_MNDR_V       MND_REG_VAL      

/* macro for writes to MSM registers */
#define MSMU_OUT( reg, val) (void)outp( reg, val)

/* macro for 16 bit writes to MSM registers */
#define MSMUW_OUT( reg, val) (void)outpw( reg, val) 

#ifdef MSMHW_UART1_512BYTE_FIFOS
#error code not present
#else

#define MSMU_RXWAT_OUT( val )    MSMU_OUT( UART_RXWAT, val )
#define MSMU_TXWAT_OUT( val )    MSMU_OUT( UART_TXWAT, val )
#define MSMU_MR1_OUT( val )      MSMU_OUT( UART_MR1, val )

#endif /* MSMHW_UART1_512BYTE_FIFOS */


/*-------------------------------------------------------------------------*/

/* Selection of which receiver status bits we consider to be errors. */

#define  UART_SR_RX_ERROR  (UART_SR_BREAK_RXD |       \
                            UART_SR_PF_ERR    |       \
                            UART_SR_OVR_ERR )

/* Setting for TX Watermark.  Set this to 30 rather than 31, because
   of the known bug in the UART. */
#define  UART_TXWAT_VAL    30

#endif /*DLOADUART_H*/