clkrgm_6000.h

在高通的手机平台下,一个下载手机.bin文件到手机的flash中的工具,包含PC端的程序代码和运行在基带处理器中的代码.

#ifndef CLKRGM_6000_H
#define CLKRGM_6000_H

/*===========================================================================

   Clock Regime MSM6000 header file

DESCRIPTION
  This header file contains all the internal target dependent definitions
  used by the DMSS clock regime services.

  Copyright (c) 1999-2002 by QUALCOMM, Incorporated.  All Rights Reserved.
===========================================================================*/

/*===========================================================================

                      EDIT HISTORY FOR FILE

This section contains comments describing changes made to this file.
Notice that changes are listed in reverse chronological order.

$Header:   L:/src/asw/MSM6000/vcs/clkrgm_6000.h_v   1.4   09 Oct 2002 16:20:36   bcalder  $   

when       who     what, where, why
--------   ---     ----------------------------------------------------------
10/09/02   bgc     Corrected bit names used on CLK_CTL8.
12/12/00   djd     Changed name from clkrgm_5105.h to clkrgm_510x.h
12/04/00   rmd     Fixed MSM_CLK_CTL7_WB__DEC_CLK_SEL_MASK redefinition.
11/22/00   et      added register definitions for the clk API changes
10/31/00   jcw     cleanup for 5105, and rearranged code
10/02/00   dsb     Created.  Includes support for MSMHW_HAS_CLK_RGM_REG_SET1,
                   which supports using a second "set" of clk regime reset &
                   enable (and optionally override) registers.
                   
===========================================================================*/

/* Rx front clock */
#define CLK_RGM_RXFRONT_SRC_TCXO_V       MSM_CLK_CTL8_WH__RX_FRONT_CLK_SEL_TCXO  
#define CLK_RGM_RXFRONT_SRC_CDMACX16_V   MSM_CLK_CTL8_WH__RX_FRONT_CLK_SEL_CDMA_CX16
#define CLK_RGM_RXFRONT_SRC_DFM_720K_V   MSM_CLK_CTL8_WH__RX_FRONT_CLK_SEL_DFM_720K 

#define CLK_RGM_RXSAMPLE_SRC_TCXO_V      MSM_CLK_CTL8_WH__RX_SAMP_CLK_SEL_TCXO
#define CLK_RGM_RXSAMPLE_SRC_CDMACX16_V  MSM_CLK_CTL8_WH__RX_SAMP_CLK_SEL_CDMA_CX16
#define CLK_RGM_RXSAMPLE_SRC_TCXODIV2_V  MSM_CLK_CTL8_WH__RX_SAMP_CLK_SEL_TCXO_DIV2
#define CLK_RGM_RXSAMPLE_SRC_TCXODIV4_V  MSM_CLK_CTL8_WH__RX_SAMP_CLK_SEL_TCXO_DIV4


/* Rx Mod clock */
#define CLK_RGM_RXMOD_SRC_TCXODIV2_V       MSM_CLK_CTL8_WH__RX_GMC_CLK_SRC_SEL_TCXO2   
#define CLK_RGM_RXMOD_SRC_TCXODIV4_V       MSM_CLK_CTL8_WH__RX_GMC_CLK_SRC_SEL_TCXO4  
#define CLK_RGM_RXMOD_SRC_GPSCX32_V        ERROR_NO_GPS_ON_MSM6000
#define CLK_RGM_RXMOD_SRC_PLLOUTDIV5_V     MSM_CLK_CTL8_WH__RX_GMC_CLK_SRC_SEL_DIV5
#define CLK_RGM_RXMOD_SRC_PLLOUTDIV10_V    ERROR_NO_PLLOUTDIV10_ON_MSM6000
#define CLK_RGM_RXMOD_SRC_PLLOUTDIV12P5_V  MSM_CLK_CTL8_WH__RX_GMC_CLK_SEL_TCXO_DIV2_5
#define CLK_RGM_RXMOD_SRC_EXT_TST_CLK_V    MSM_CLK_CTL8_WH__RX_GMC_CLK_SEL_GPIO50
#define CLK_RGM_RXMOD_SRC_GROUND_V         ERROR_NO_GROUND_ON_MSM6000


#ifdef MSMHW_CHIPX8_BYPASS
#define CLK_RXCX8_BYPASS_REG MSM_CLK_CTL1_WH
#endif

#ifndef MSMHW_NO_SRCH2_CLK_RGM
#define CLK_RGM_SRCH2_M      (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x0400) /* Searcher2 (16x) */
#endif

#ifdef MSMHW_GPS
#error code not present
#endif 



#ifdef MSMHW_DEC_CLK_RGM
#define CLK_RGM_DEC_REG      MSM_CLK_CTL1_WH
#endif /* MSMHW_DEC_CLK_RGM */

#ifdef FEATURE_SEARCH2
#ifdef MSMHW_NO_SRCH2_CLK_RGM

#else
#define CLK_RGM_CHIPX8_M     ( CLK_RGM_CDMA_TX_M | \
                               CLK_RGM_CDMA_RX8_M | \
                               CLK_RGM_CDMA_RXDSP_M | \
                               CLK_RGM_SRCH2_M | \
                               CLK_RGM_CDMA_AGC_M | \
                               CLK_RGM_CDMA_PDM_M )
#endif /* MSMHW_NO_SRCH2_CLK_RGM */
#else
#endif /* FEATURE_SEARCH2 */

#ifdef FEATURE_SEARCH2
#ifdef MSMHW_NO_SRCH2_CLK_RGM
#else
#define CLK_RGM_CDMA_RX_M    ( CLK_RGM_CDMA_RX8_M | \
                               CLK_RGM_CDMA_RXDSP_M | \
                               CLK_RGM_SRCH2_M | \
                               CLK_RGM_CDMA_AGC_M | \
                               CLK_RGM_CDMA_PDM_M )
#endif /* MSMHW_NO_SRCH2_CLK_RGM */
#else
#endif /* FEATURE_SEARCH2 */



/***
 * Define CLOCK regimes and their respective source.
 ***/
#define CLK_RGM_ENABLE     0x0000
#define CLK_RGM_DISABLE    0xFFFF
#define CLK_RGM_CLEAR      0x0000
#define CLK_RGM_SET        0xFFFF
#define CLK_RGM_MISC_ENA   0xFF
#define CLK_RGM_MISC_DIS   0x00

/* Masks */

/*
** CLK_CTL1 Clock Regime Management Register masks
** CLK_CTL2 Overriden Clock Control Register masks
*/

#define CLK_RGM_ALL_SET0_M   0xFF7F /* Bit:7 internal use */
#define CLK_RGM_ALL_SET1_M   0xFFFF

#define CLK_RGM_GEN_REG      MSM_CLK_CTL1_WH
#define CLK_RGM_UART_REG     MSM_CLK_CTL1_WH
#define CLK_RGM_CDMA_TX_REG  MSM_CLK_CTL1_WH
#define CLK_RGM_CDMA_RX8_REG MSM_CLK_CTL1_WH
#define CLK_RGM_DFM_REG      MSM_CLK_CTL1_WH
#define CLK_RGM_COD_REG      MSM_CLK_CTL1_WH
#define CLK_RGM_VOC_REG      MSM_CLK_CTL1_WH
/* Bit:7 INTERNAL USE only */
#define CLK_RGM_SBI_REG      MSM_CLK_CTL1_WH
#define CLK_RGM_CDMA_RXDSP_REG MSM_CLK_CTL1_WH
#define CLK_RGM_SRCH2_M      (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x0400) /* Searcher2 (16x) */
#define CLK_RGM_GPS_M        (((MSM_CLK_CTL1_WH & 0xffff) << 16) | 0x0800) /* GPS */
#define CLK_RGM_COD_CORE_REG MSM_CLK_CTL1_WH
#define CLK_RGM_USB_REG      MSM_CLK_CTL1_WH
#define CLK_RGM_CDMA_AGC_REG MSM_CLK_CTL1_WH
#define CLK_RGM_CDMA_PDM_REG MSM_CLK_CTL1_WH

#define RXCX8_MICRO_BYPASS_REG  MSM_CLK_CTL1_WH

/* New clock regimes */
/* CLK regime set 1 */
#define CLK_RGM1_BT_M        (((MSM_CLK_CTL7_WH & 0xffff) << 16) | 0x0001) /* Bluetooth */
#define CLK_RGM1_BT_REG      MSM_CLK_CTL7_WH
#define CLK_RGM1_SDAC_M      (((MSM_CLK_CTL7_WH & 0xffff) << 16) | 0x0002) /* Stereo DAC */
#define CLK_RGM1_SDAC_REG    MSM_CLK_CTL7_WH
#define CLK_RGM1_MMC_DIV_M   (((MSM_CLK_CTL7_WH & 0xffff) << 16) | 0x0003) /* MMC Div */
#define CLK_RGM1_MMC_DIV_REG MSM_CLK_CTL7_WH


/*
** CLK_CTL3 Clock Regime Reset Register masks
*/
#define CLK_RGM_GEN_RESET_M        0x0001 /* Timetick, Ringer, PDM1,2, YAMN1 */
#define CLK_RGM_GEN_RESET_REG      MSM_CLK_CTL3_WH
#define CLK_RGM_UART_RESET_M       0x0002 /* UART, HKADC Intf */
#define CLK_RGM_UART_RESET_REG     MSM_CLK_CTL3_WH
#define CLK_RGM_CDMA_TX_RESET_M    0x0004 /* Modulator, Interleaver */
#define CLK_RGM_CDMA_TX_RESET_REG  MSM_CLK_CTL3_WH
#define CLK_RGM_CDMA_RX_RESET_M    0x0008 /* Searcher, Combiner, FFE */   
#define CLK_RGM_CDMA_RX_RESET_REG  MSM_CLK_CTL3_WH
#define CLK_RGM_DFM_RESET_M        0x0010 /* DFM Core, PDMs */
#define CLK_RGM_DFM_RESET_REG      MSM_CLK_CTL3_WH
#define CLK_RGM_COD_RESET_M        0x0020 /* PCM CODEC Intf */
#define CLK_RGM_COD_RESET_REG      MSM_CLK_CTL3_WH
#define CLK_RGM_VOC_RESET_M        0x0040 /* Vocoder */ 
#define CLK_RGM_VOC_RESET_REG      MSM_CLK_CTL3_WH
#define CLK_RGM_SLEEP_RESET_M      0x0080 /* Sleep Cntr, Watch-Dog */
#define CLK_RGM_SLEEP_RESET_REG    MSM_CLK_CTL3_WH
#define CLK_RGM_SBI_RESET_M        0x0100 /* SBI Intf */ 
#define CLK_RGM_SBI_RESET_REG      MSM_CLK_CTL3_WH
#define CLK_RGM_CDMA_RXDSP_RESET_M 0x0200 /* Decoder(Deinterleaver), DemodDSP */
#define CLK_RGM_CDMA_RXDSP_RESET_REG MSM_CLK_CTL3_WH
#define CLK_RGM_SRCH2_RESET_M      0x0400 /* Searcher2 (16x) */
#define CLK_RGM_SRCH2_RESET_REG    MSM_CLK_CTL3_WH
#define CLK_RGM_GPS_RESET_M        0x0800 /* GPS */
#define CLK_RGM_GPS_RESET_REG      MSM_CLK_CTL3_WH
#define CLK_RGM_COD_CORE_RESET_M   0x1000 /* CODEC Core */
#define CLK_RGM_COD_CORE_RESET_REG MSM_CLK_CTL3_WH
#define CLK_RGM_USB_RESET_M        0x2000 /* USB */
#define CLK_RGM_USB_RESET_REG      MSM_CLK_CTL3_WH
#define CLK_RGM_CAGC_RESET_M       0x4000 /* CDMA AGC, Rx PDMs */
#define CLK_RGM_CAGC_RESET_REG     MSM_CLK_CTL3_WH
#define CLK_RGM_PDM_RESET_M        0x8000 /* Rx and Tx PDMs */
#define CLK_RGM_PDM_RESET_REG      MSM_CLK_CTL3_WH

/*
** MISC_CTL Misc Clock Regime Register masks
*/
#define CLK_RGM_MISC_ALL_Mi           0x0f  /* Bits d0:d3 */
#define CLK_RGM_MISC_AGC_SLEEP_ENA_Mi 0x08  /* AGC Sleep enable  if set (1) */
#define CLK_RGM_MISC_PDM_SLEEP_ENA_Mi 0x04  /* PDM Sleep enable  if set (1) */
#define CLK_RGM_MISC_TCXO_AC_Mi       0x02  /* TCXO Pad AC mode  if set (1) */
#define CLK_RGM_MISC_TXDAC_SLEEP_Mi   0x01  /* TXDAC pwr up/down if set (1) */

#define CLK_RGM_MISC_PLLOUTDIV5_ENA_Mi         MSM_CLK_CTL8_WH__DIV5_EN_MASK

/* The mapping below of MOD_CLK to GMC_CLK is needed because RF wants 6050 and 6000 
 * to have same interface for MISC_CTL.
*/
#define CLK_RGM_MISC_RX_MOD_CLK_Mi             MSM_CLK_CTL8_WH__RX_GMC_CLK_EN_MASK 
#define CLK_RGM_MISC_RX_MOD_CLK_DIFF_OUT_Mi    MSM_CLK_CTL8_WH__RX_GMC_CLK_DIFF_SEL_MASK 
#define CLK_RGM_MISC_RX_TCXO_Mi                MSM_CLK_CTL8_WH__RX_MOD_CLK_EN_MASK 
#define CLK_RGM_MISC_RX_TCXO_CLK_DIFF_OUT_Mi   MSM_CLK_CTL8_WH__RX_MOD_CLK_DIFF_SEL_MASK 

typedef enum {
  /* misc_ctl registers */
CLK_RGM_MISC_ALL_M,
CLK_RGM_MISC_AGC_SLEEP_ENA_M,
CLK_RGM_MISC_PDM_SLEEP_ENA_M,
CLK_RGM_MISC_TCXO_AC_M,
CLK_RGM_MISC_TXDAC_SLEEP_M,
  /* msm_clk_ctl8 registers */
CLK_RGM_MISC_PLLOUTDIV5_ENA_M,
CLK_RGM_MISC_RX_MOD_CLK_M,
CLK_RGM_MISC_RX_MOD_CLK_DIFF_OUT_M,
CLK_RGM_MISC_RX_TCXO_M,
CLK_RGM_MISC_RX_TCXO_CLK_DIFF_OUT_M
} clk_regime_misc_type;

/*
**MSM_CLK_CTL5 registers.  the masks are in msm6000bits.h
*/

#define DEC_CLK_SEL_M                       MSM_CLK_CTL7_WH__DEC_CLK_SEL_MASK
#define DEC_CLK_SEL_REG                     MSM_CLK_CTL7_WH

#define UART_CLK_SEL_M                      MSM_CLK_CTL7_WH__UART_CLK_SEL_MASK
#define UART_CLK_SEL_REG                    MSM_CLK_CTL7_WH
#define UART_CLK_SEL_TCXO4                  MSM_CLK_CTL7_WH__UART_CLK_SEL_TCXO4


#define  SLEEP_4M_32K_SEL_M                 MSM_CLK_CTL5_WH__SLEEP_4M_32K_SEL_MASK
#define  SLEEP_4M_32K_SEL_REG               MSM_CLK_CTL5_WH
#define  SLEEP_4M_32K_SEL_32K               MSM_CLK_CTL5_WH__SLEEP_4M_32K_SEL_32K

#define  VOC_CLK_DIV_DIV1_REG               MSM_CLK_CTL5_WH

#define VOC_CLK_SEL_TXCO_M                  MSM_CLK_CTL5_WH__VOC_CLK_SEL_TXCO 
#define VOC_CLK_SEL_TXCO_REG                MSM_CLK_CTL5_WH

#define QDSP2_CODEC_EN_N_REG                MSM_CLK_CTL5_WH

#define GENERAL_CLK_SEL_TCXO4_M             MSM_CLK_CTL5_WH__GENERAL_CLK_SEL_TCXO4
#define GENERAL_CLK_SEL_TCXO4_REG           MSM_CLK_CTL5_WH

#define USB_OSC_RD_BYPASS_REG               MSM_CLK_CTL5_WH





#define USB_OSC_RF_BYPASS_M             (((MSM_CLK_CTL5_WH & 0xffff) << 16) | MSM_CLK_CTL5_WH__USB_OSC_RF_BYPASS_MASK) 
#define USB_OSC_RF_BYPASS_REG           MSM_CLK_CTL5_WH
#define USB_OSC_GAIN_MIN_M                  (((MSM_CLK_CTL5_WH & 0xffff) << 16) | MSM_CLK_CTL5_WH__USB_OSC_GAIN_MIN) 
#define USB_OSC_GAIN_MIN_REG                MSM_CLK_CTL5_WH
#define USB_OSC_EN_N_REG                MSM_CLK_CTL5_WH
#define SLEEP_4M_32K_SEL_32K_M              MSM_CLK_CTL5_WH__SLEEP_4M_32K_SEL_32K
#define SLEEP_4M_32K_SEL_32K_REG            MSM_CLK_CTL5_WH

#define CDMA_RXDSP_CLK_SEL_TCXO23_M         MSM_CLK_CTL7_WH__CDMA_RXDSP_CLK_SEL_TCXO23
#define CDMA_RXDSP_CLK_SEL_TCXO23_REG       MSM_CLK_CTL7_WH

#define UART_SBI_CLK_SEL_TCXO4_M            MSM_CLK_CTL7_WH__UART_SBI_CLK_SEL_TCXO4 
#define UART_SBI_CLK_SEL_TCXO4_REG          MSM_CLK_CTL7_WH

#define SLEEP_4M_32K_SEL_4M_M               MSM_CLK_CTL5_WH__SLEEP_4M_32K_SEL_4M
#define SLEEP_4M_32K_SEL_4M_REG             MSM_CLK_CTL5_WH

/*
**MSM_CLK_CTL7 registers.  the masks are in msm6000bits.h
*/
#define SBI_CLK_SEL_M      MSM_CLK_CTL7_WH__SBI_CLK_SEL_MASK
#define SBI_CLK_SEL_REG   MSM_CLK_CTL7_WH
#define SBI_CLK_SEL_TCXO4 MSM_CLK_CTL7_WH__SBI_CLK_SEL_TCXO4

#ifdef MSMHW_INTERNAL_STEREO_DAC
#error code not present
#endif

/*
**MSM_CLK_CTL8 registers.  the masks are in msm6000bits.h
*/
#define SDAC_CLK_M         (((MSM_CLK_CTL7_WH & 0xffff) << 16) | MSM_CLK_CTL8_WH__SDAC_CLK_MASK)
#define SDAC_CLK_REG      MSM_CLK_CTL8_WH

#endif /* CLKRGM_6000_H */