📄 boothwi_6000.h
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It does not matter for RAM 2 because RAM2_CS is disabled */
#define SRAM_PCS6_CFG ( (((~(RAM2_BSIZE_EN) & 0x01)) << 1) | (~(RAM1_BSIZE_EN) & 0x01))
/* Bit [12] When this bit is set, MSM3000-type by 16 sram support is enabled */
/* Send LB_N to RAM2_CS/GPIO_INT37 PIN*/
#define BY16SRAM_ONLY 0x01
/* if LB_N (low byte enable) comes out of GPIO_INT12 PIN */
#elif defined(T_LBN_ON_GPIO_INT12_PIN)
/* Bit [10:9] Sets RAM 1 and RAM 2 to 16 bits or 8 bits. */
/* Select 16 bit/8 bit access for RAM 1 and RAM 2 */
#define SRAM_PCS6_CFG ( (((~(RAM2_BSIZE_EN) & 0x01)) << 1) | (~(RAM1_BSIZE_EN) & 0x01) )
/* Bit [12] When this bit is set, MSM3000-type by 16 sram support is enabled */
/* Send LB_N to GPIO_INT12 PIN*/
#define BY16SRAM_ONLY 0x00
/* if LB_N is not assigned to a pin */
#else
/* Bit [10:9] Sets RAM 1 and RAM 2 to 16 bits or 8 bits.*/
/* Because LB_N is not coming out off any pin then we
most have 8 bit access on both RAM 1 and RAM 2 */
#define SRAM_PCS6_CFG 0x00
/* Bit [12] When this bit is set, MSM3000-type by 16 sram support is enabled */
/* Send LB_N to GPIO_INT12 PIN, Just init it to something */
#define BY16SRAM_ONLY 0x00
#endif
/*----------------------------------------------------------------------------
ASB Decode Control
----------------------------------------------------------------------------*/
// Bit [0] ASB_DECODE_CTL if set will force the decoder to add a decode cycle
// to all subsequent access
#if defined (DEBUG_ICE_MODE)
#define ASB_DECODE_CTL_WAIT 0x01
#else
#define ASB_DECODE_CTL_WAIT 0x00
#endif
//--------------------------------------------------------------------------
// TLMM Functions - Will Override GPIO pin functionality
// GPIO_INT_FUNCTION_SEL_0_WH, GPIO_INT_FUNCTION_SEL_1_WH
//--------------------------------------------------------------------------
/* SLOTTED_FM_MODE is used in conjunction with an interrupt to the ARM
** processor, to power off additional RF circuits to save power.
** signals affected: FM_RF_SLEEP_N
*/
#define SLOTTED_FM_MODE FALSE
/* GPIO_UART allows the user to select whether a second uart is to be
** brought out on the GPIO lines or the AUX_PCM pins.
** signals affected: CTS_N2, RFR_N2, DP_RX_DATA2,DP_TX_DATA2
*/
#if defined(FEATURE_UIM)
#define GPIO_UART FALSE
#else
#define GPIO_UART FALSE
#endif
/* ROM2_CS is used as the Chip Select signal for the second flash memory
** chip.
** signals affected: EEPROM_CS_N
*/
#if defined (FEATURE_EFS) && !defined(LT_LOUIS_DRV_ACCESSORY)
#define ROM2_CS TRUE
#else
#define ROM2_CS FALSE
#endif
/* LCD_CS_ENABLE enables the external LCD support lines
** signals affected: LCD_CS_N, LCD_EN
*/
#define LCD_CS_ENABLE FALSE
/* GP_CS_ENABLE enables support for the GP_CS signal
** signals affected: GP_CS_N
*/
#if defined(LT_LOUIS_DRV_ACCESSORY)
#define GP_CS_ENABLE FALSE
#elif (defined TIMETEST) || (defined TRAMP_INT_TIMING_TEST) || (defined RUIM_DRIVER_TIME_TEST)
#define GP_CS_ENABLE TRUE
#else
#define GP_CS_ENABLE FALSE
#endif
#ifdef T_IO_CARD
#define MUX_TX_IQ_DATA_EN TRUE
#else
#define MUX_TX_IQ_DATA_EN FALSE
#endif
// EXTENDED_ADDR brings out the A21,A22 to the external peripheral bus
// signals affected: A21, A22
// 0 ... NO extended addressing
// 1 ... extended addressing
#define EXTENDED_ADDR 0
/*----------------------------------------------------------------------------
GPIO FUNCTION Select
----------------------------------------------------------------------------*/
/* If LB_N (low byte enable) comes out of RAM2_CS signal*/
#if defined(T_LBN_ON_RAM2_CS_PIN)
/* Enable RAM2_CS signal on GPIO_INT37 pin*/
#define GPIO_INT_FUNCTION_SEL_0__PCS6_CS_SEL_VAL GPIO_INT_FUNC_SEL_0_PCS6_CS_ENA
/* LB_N is coming out of of RAM2_CS/GPIO_INT37 pin so disable LB_N
on GPIO_INT12 pin */
#define GPIO_INT_FUNCTION_SEL_1__LB_N_SEL_VAL GPIO_INT_FUNC_SEL_1_LB_N_DIS
/* If LB_N (low byte enable) comes out of GPIO_INT12*/
#elif defined(T_LBN_ON_GPIO_INT12_PIN)
/* We are not using RAM2_CS so we have the option of having RAM 2 */
#if defined(T_SRAM2_PRESENT)
/* Enable RAM2_CS for RAM 2*/
#define GPIO_INT_FUNCTION_SEL_0__PCS6_CS_SEL_VAL GPIO_INT_FUNC_SEL_0_PCS6_CS_ENA
#else
/* Disable RAM2_CS, RAM 2 not present*/
#define GPIO_INT_FUNCTION_SEL_0__PCS6_CS_SEL_VAL GPIO_INT_FUNC_SEL_0_PCS6_CS_DIS
#endif /*T_SRAM2_PRESENT*/
/* Enable LB_N on GPIO_INT12 pin*/
#define GPIO_INT_FUNCTION_SEL_1__LB_N_SEL_VAL GPIO_INT_FUNC_SEL_1_LB_N_ENA
/* If LB_N is not assigned to a pin*/
#else
/* We are not using RAM2_CS so we have the option of having RAM 2 */
#if defined(T_SRAM2_PRESENT)
/* Enable RAM2_CS for RAM 2*/
#define GPIO_INT_FUNCTION_SEL_0__PCS6_CS_SEL_VAL GPIO_INT_FUNC_SEL_0_PCS6_CS_ENA
#else
/* Disable RAM2_CS, RAM 2 not present*/
#define GPIO_INT_FUNCTION_SEL_0__PCS6_CS_SEL_VAL GPIO_INT_FUNC_SEL_0_PCS6_CS_DIS
#endif /*T_SRAM2_PRESENT*/
/* Disable LB_N on GPIO_INT12 pin*/
#define GPIO_INT_FUNCTION_SEL_1__LB_N_SEL_VAL GPIO_INT_FUNC_SEL_1_LB_N_DIS
#endif
/*---------------------------------------------------------------------------
INTERNAL MACROS
---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------
MACRO BOOT_HW_GPIO_FUNC_SEL0_VAL
This macro creates the initial value for GPIO_INT_FUNCTION_SEL_0.
---------------------------------------------------------------------------*/
#define BOOT_HW_GPIO_FUNC_SEL0_VAL \
(GPIO_INT_FUNCTION_SEL_0__PCS6_CS_SEL_VAL | \
(MUX_TX_IQ_DATA_EN ? GPIO_INT_FUNC_SEL_0_WH__TX_DATA_SEL__TX_IQDATA : \
GPIO_INT_FUNC_SEL_0_WH__TX_DATA_SEL__GPIO_INT) | \
(ROM2_CS ? GPIO_INT_FUNCTION_SEL_0_WH__EEPROM_CS_SEL_MASK :0)| \
(LCD_CS_ENABLE ? (GPIO_INT_FUNCTION_SEL_0_WH__LCD_CS_SEL_MASK | \
GPIO_INT_FUNCTION_SEL_0_WH__LCD_EN_SEL_MASK) :0)| \
(GP_CS_ENABLE ? GPIO_INT_FUNCTION_SEL_0_WH__GP_CS_SEL_MASK :0) )
/*---------------------------------------------------------------------------
MACRO BOOT_HW_GPIO_FUNC_SEL1_VAL
This macro creates the initial value for GPIO_INT_FUNCTION_SEL_1.
---------------------------------------------------------------------------*/
#define BOOT_HW_GPIO_FUNC_SEL1_VAL \
(GPIO_INT_FUNCTION_SEL_1__LB_N_SEL_VAL | \
(SLOTTED_FM_MODE ? GPIO_INT_FUNCTION_SEL_1_WH__GPIO_INT13_SEL_MASK :0) |\
(GPIO_UART ? GPIO_INT_FUNCTION_SEL_1_WH__GPIO_UART2_SEL_MASK :0))
/*---------------------------------------------------------------------------
MACRO BOOT_HW_GPIO_FUNC_SEL2_VAL
This macro creates the initial value for GPIO_INT_ADDR_SEL.
---------------------------------------------------------------------------*/
#ifdef MSMHW_MSM6000_CLK2
/* Set GPIO50 to output chipX16. */
#define BOOT_HW_GPIO_FUNC_SEL2_VAL 0x100
#else
#define BOOT_HW_GPIO_FUNC_SEL2_VAL 0
#endif /* MSMHW_MSM6000_CLK2 */
/*---------------------------------------------------------------------------
MACRO BOOT_HW_GPIO_FUNC_SEL_INIT
This Macro Fills the array GpioFuncSelInit[] in boothw_6000.c with the addr
and value for each register that needs to be initialized to provide initial
functionality to selected gpio pins.
---------------------------------------------------------------------------*/
#define BOOT_HW_GPIO_FUNC_SEL_INIT \
{(dword)GPIO_INT_FUNCTION_SEL_0_WH, BOOT_HW_GPIO_FUNC_SEL0_VAL}, \
{(dword)GPIO_INT_FUNCTION_SEL_1_WH, BOOT_HW_GPIO_FUNC_SEL1_VAL}, \
{(dword)GPIO_INT_FUNCTION_SEL_2_WH, BOOT_HW_GPIO_FUNC_SEL2_VAL}, \
{(dword)NULL, 0}
/*---------------------------------------------------------------------------
MACRO BOOT_HW_SET_WAIT_STATES_TCXO
Setup MSM6000 memory wait states
---------------------------------------------------------------------------*/
//#define BOOT_HW_SET_WAIT_STATES_TCXO() // \
// outpw (MEMORY_WAIT1_WH, 0x2023);//\
// // \
// outpw (MEMORY_WAIT2_WH, 0x824) //(RAM2_BASE<<8) | //\
//(RAM1_MIN_ACCESS << 4) | // \
//(RAM2_MIN_ACCESS) )
#endif /*BOOTHWI_6000_H*/
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