📄 boothwi_6000.h
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#ifndef BOOTHWI_6000_H
#define BOOTHWI_6000_H
/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
B O O T H A R D W A R E M S M 6 0 0 0 S P E C I F I C
I N I T I A L I Z A T I O N H E A D E R
GENERAL DESCRIPTION
This header file contains Configuration Constants as well as and Internal
Macro definitions specific for the MSM6000. These definitions can not be used
by other modules in DMSS.
Copyright (c) 1991-2002 by QUALCOMM Incorporated.
All Rights Reserved.
*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
/*===========================================================================
EDIT HISTORY FOR MODULE
This section contains comments describing changes made to the module.
Notice that changes are listed in reverse chronological order.
$Header: L:/src/asw/MSM6000/vcs/boothwi_6000.h_v 1.5 31 Oct 2002 14:42:22 bcalder $
when who what, where, why
-------- ------- ----------------------------------------------------------
04/19/05 gx.jiang Modified memeory wait state
02/18/05 nony.wu Edit rom wait state
02/03/05 gx.jiang Fixed the setting bug.
01/14/05 gx.jiang Modified the CS, waiting sate and TLMM setting for the
Leadtech Louis board.
-------- ------- ----------------------------------------------------------
10/09/01 bgc Added MSMHW_MSM6000_CLK2 to select GPIO50 as clock output
for ChipX16 for syncronization of clocks in RXF.
03/21/01 hjr Removed legacy code.
04/06/01 djd Merged changes to support T_MB_SURF_4100.
01/17/00 rmd Updated SRAM_PCS6_CFG definition.
12/12/00 djd Changed name from boothwi_5105.h to boothwi_510x.h
12/04/00 djd Changed DEBUG_IO_CARD to T_IO_CARD
11/21/00 rmd Moved to the clk regime code, the initialization of:
MSM_CLK_CTL6_WH, CDMA MND counter and GPS MND counter.
Added support to 4/3 TCXO.
11/09/00 rmd Removed GPIO_INT_FUNC_SEL_0_WH__TX_DATA_SEL__TX_DATA_SEL_VAL
from the GPIO_INT_FUNCTION_SEL0_VAL Macro and replaced it with
(GPIO_INT_FUNC_SEL_0_WH__TX_DATA_SEL__TX_IQDATA or
GPIO_INT_FUNC_SEL_0_WH__TX_DATA_SEL__GPIO_INT) depending if
DEBUG_IO_CARD is defined or not.
11/06/00 rmd Replaced FEATURE_IO_CARD with DEBUG_IO_CARD which is defined
in debug.h.
11/01/00 rmd Small code clean up.
10/31/00 et Added GPIO_INT_FUNC_SEL_0_WH__TX_DATA_SEL__TX_DATA_SEL_VAL
to the GPIO_INT_FUNCTION_SEL0_VAL Macro.
11/01/00 rmd Made changes to BOOT_HW_ENA_CHIPXN_CLK_TO_XXXX macros to
merge with MSM3300. Also, created BOOT_HW_SET_GPS_MND_COUNTER
macro.
10/13/00 rmd Initial Revision
===========================================================================*/
/*------------------------------------------------------------------------------
ASB Register Defines
------------------------------------------------------------------------------
----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
ASB Memory Wait 1
----------------------------------------------------------------------------*/
// Bit [3..0] EEPROM Minimum number of Cycles used on 16 bit access
#if defined (DEBUG_ICE_MODE)
#define ROM2_HWORD_WAIT 0x2
#else
#define ROM2_HWORD_WAIT 0x3
#endif
// Bit [7..4] ROM Minimum number of Cycles used on 16 bit access
#if defined (DEBUG_ICE_MODE)
#define ROM1_HWORD_WAIT 0x2
#else
#define ROM1_HWORD_WAIT 0x2
#endif
/*----------------------------------------------------------------------------
ASB Memory Wait 2
----------------------------------------------------------------------------*/
// Bit [3..0] PCS6 Minimum number of cycles inserted on access to PCS6_N
#if defined (DEBUG_ICE_MODE)
#define RAM2_MIN_ACCESS 2
#else
#define RAM2_MIN_ACCESS 3
#endif
// Bit [7..4] RAM Minimum number of Cycles inserted on access to RAM_CS_N
#if defined (DEBUG_ICE_MODE)
#define RAM1_MIN_ACCESS 2
#else
#define RAM1_MIN_ACCESS 2
#endif
/*----------------------------------------------------------------------------
Bus Sizer Control 1
----------------------------------------------------------------------------*/
// Bit [2..0] EEPROM_CS_N extra clock cycles added to the beginning of a read
// from EEPROM_CS_N
#define ROM2_RD_CNT 0x00
// Bit [5..3] EEPROM_CS_N extra clock cycles added to the beginning of a write
// to EEPROM_CS_N
#define ROM2_WR_CNT 0x00
// Bit [8..6] ROM_CS_N extra clock cycles added to the beginning of a read
// from ROM_CS_N
#define ROM1_RD_CNT 0x00
// Bit [11..9] ROM_CS_N extra clock cycles added to the beginning of a write
// from ROM_CS_N
#define ROM1_WR_CNT 0x00
/*----------------------------------------------------------------------------
General Purpose Chip Select Wait States
----------------------------------------------------------------------------*/
// Bit [4..0] GP_CS_N_WAIT number of wait states inserted during a GP_CS_N
#define GP_ACCESS 0x01 //Base addr of 256Kbytes
// Bit [9..5] GP_CS_N_WAIT number of wait states inserted during a GP2_CS_N
#define GP2_ACCESS 0x01
// Bit [14..10] GP_CS_N_WAIT base address of GP2_CS_N
#define GP2_BASE 0x01
/*----------------------------------------------------------------------------
Bus Sizer Control 2
----------------------------------------------------------------------------*/
// Bit [2..0] PCS6_RD_CNT extra clock cycles added to the beginning of a read
// from PCS6_N
#define RAM2_RD_CNT 0x00
// Bit [5..3] PCS6_WR_CNT extra clock cycles added to the beginning of a write
// to PCS6_N
#define RAM2_WR_CNT 0x00
// Bit [8..6] RAM_RD_CNT extra clock cycles added to the beginning of a read
// from RAM_CS_N
#define RAM1_RD_CNT 0x00
// Bit [11..9] RAM_WR_CNT extra clock cycles added to the beginning of a write
// to RAM_CS_N
#define RAM1_WR_CNT 0x00
// Bit [12] PCS6_BSIZE_EN Enable or Disable 8-bit Bus sizing for PCS6_N
#if defined(LT_LOUIS_DRV_ACCESSORY)
#define RAM2_BSIZE_EN 1
#else
#define RAM2_BSIZE_EN 0
#endif
// Bit [13] RAM_BSIZE_EN Enable or Disable 8-bit Bus sizing for RAM_CS_N
#define RAM1_BSIZE_EN 0
/*----------------------------------------------------------------------------
LCD Control
----------------------------------------------------------------------------*/
// Bit [3..0] LCD_E_HIGH how many clock cycles are used on from LCD_E pin
// asserting high to LCD_E de-asserting low
#define LCD_E_HIGH 0x03
// Bit [7..4] LCD_E_SETUP how many clock cycles are used on from the start
// of LCD_CS_N access to LCD_E pin asserting high
#define LCD_E_SETUP 0x01
// Bit [12..8] LCD_ACCESS how many clock cycles are used on a 16 bit access
// to LCD_CS_N
#define LCD_ACCESS 0x05
/*----------------------------------------------------------------------------
Chip Select Control
----------------------------------------------------------------------------*/
// Bit [0] EEPROM_CS_EN
#if defined (FEATURE_EFS) && !defined(LT_LOUIS_DRV_ACCESSORY)
#define ROM2_CS_EN 1
#else
#define ROM2_CS_EN 0
#endif
// Bit [1] RAM_CS_EN
#define RAM1_CS_EN 1
#if defined(LT_LOUIS_DRV_ACCESSORY)
// Bit [2] PCS6_EN
#define RAM2_CS_EN 1
#else
#define RAM2_CS_EN 0
#endif
// Bit [3] LCD_CS_EN
#define LCD_CS_EN 0
// Bit [4] LCD_E
#define LCD_E_EN 0
// Bit [5] GP_CS_EN
#if !defined(LT_LOUIS_DRV_ACCESSORY)
#define GP_CS_EN 1
#else
#define GP_CS_EN 0
#endif
// Bit [6] RESERVED
// Bit [7] RESERVED
/* Bit [11] This bit enables the second general purpose chip select GP2_CS_n */
#define GP2_CS_EN 0x00
/* if LB_N (low byte enable) comes out of RAM2_CS/GPIO_INT37 PIN */
#if defined(T_LBN_ON_RAM2_CS_PIN)
/* Bit [10:9] Sets RAM 1 and RAM 2 to 16 bits or 8 bits.*/
/* Select 16 bit/8 bit access for RAM 1 and RAM 2
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