clk_origin.vhd

来自「计数时钟芯片代码」· VHDL 代码 · 共 35 行

--CLK DIVIVE IN TO 8Hz
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_origin is
    Port ( CLK : in std_logic;
           PCLK : out std_logic);
end clk_origin;

architecture main of clk_origin is

signal c:integer range 0 to 2047:=0;	 --这里不能有空格，否则出错！晕
signal PCLKi:std_logic:='0';

begin
PCLK<=PCLKi;
process(CLK)
begin
	if(CLK'event and CLK='1') then
		if(c=2047) then 
			PCLKi<=not PCLKi;
			c<=0;
		else c<=c+1; 	
		end if;
	end if;
end process;
end main;