ck20_top.vhd

计数时钟芯片代码

------------------------------------------------------------------
library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all; 
use IEEE.std_logic_unsigned.all; 
  
-----------------------------ENTITY DECLARATION-----------------------

entity ck20_top is
  port (
        DBUS : in std_logic_vector(7 downto 0);
        RST : in std_logic;
        ALE : in std_logic;
	WR : in std_logic;
	CS : in std_logic_vector(1 downto 0);
	CLK : in std_logic;
	H1  : out std_logic_vector(1 downto 0);
	H0  : out std_logic_vector(3 downto 0);
	SEC : out std_logic;
	MIN1: out std_logic_vector(2 downto 0);
	MIN0: out std_logic_vector(3 downto 0)
	);
end ck20_top;


architecture struc of ck20_top is
                              
-- Signals for ck20_top connection

         Signal sc_DBUS     	 : std_logic_vector(7 downto 0);
         Signal sc_RST     	   : std_logic;
         Signal sc_ALE     	   : std_logic;
         Signal sc_WR     	   : std_logic;   
         Signal sc_CS     	   : std_logic_vector(1 downto 0);
         Signal sc_CLK     	   : std_logic;
         Signal sc_H1     	   : std_logic_vector(1 downto 0);
         Signal sc_H0     	   : std_logic_vector(3 downto 0);
         Signal sc_SEC     	   : std_logic;
         Signal sc_MIN1     	 : std_logic_vector(2 downto 0);
         Signal sc_MIN0     	 : std_logic_vector(3 downto 0);


-- Signals for ck20 connection

         Signal sc_ck20_DBUS     	 : std_logic_vector(7 downto 0);
         Signal sc_ck20_RST     	 : std_logic;
         Signal sc_ck20_ALE     	 : std_logic;
         Signal sc_ck20_WR     	 : std_logic;   
         Signal sc_ck20_CS     	 : std_logic_vector(1 downto 0);
         Signal sc_ck20_CLK     	 : std_logic;
         Signal sc_ck20_H1     	 : std_logic_vector(1 downto 0);
         Signal sc_ck20_H0     	 : std_logic_vector(3 downto 0);
         Signal sc_ck20_SEC     	 : std_logic;
         Signal sc_ck20_MIN1     	 : std_logic_vector(2 downto 0);
         Signal sc_ck20_MIN0     	 : std_logic_vector(3 downto 0);


         Signal st_0 : std_logic;
         Signal st_1 : std_logic;
         
         
  -- PAD for normal I/O
  component PLBI8N 
    port (
          D     : out std_logic;
	        P     : inout std_logic;
	        A     : in std_logic;
	        CONOF : in std_logic;
	        NEN   : in std_logic;
	        PD    : in std_logic;
	        PEN   : in std_logic;
	        PU    : in std_logic;
	        SONOF : in std_logic
        );
  end component;         

 component ck20
    port ( 
      DBUS 	: in std_logic_vector(7 downto 0);
      RST 	: in std_logic;
      ALE 	: in std_logic;
      WR 	: in std_logic;
      CS 	: in std_logic_vector(1 downto 0);
      CLK 	: in std_logic;
      H1  	: out std_logic_vector(1 downto 0);
      H0  	: out std_logic_vector(3 downto 0);
      SEC 	: out std_logic;
      MIN1	: out std_logic_vector(2 downto 0);
      MIN0	: out std_logic_vector(3 downto 0)
		 );
end component;







         
         
begin                

  inst_ck20 : ck20
  port map(            
           DBUS       =>      sc_ck20_DBUS,
           RST        =>      sc_ck20_RST,
           ALE        =>      sc_ck20_ALE,
           WR         =>      sc_ck20_WR,
           CS         =>      sc_ck20_CS,
           CLK        =>      sc_ck20_CLK,
           H1         =>      sc_ck20_H1,
           H0         =>      sc_ck20_H0,
           SEC        =>      sc_ck20_SEC,
           MIN1       =>      sc_ck20_MIN1,
           MIN0       =>      sc_ck20_MIN0
           );

  -- Constant '1' and '0' define
  st_0 <= '0';
  st_1 <= '1'; 
   
 
   -- Input : DBUS(0) pin --	
    i_PAD_DBUS_0 : PLBI8N
    port map(
      	     D  => sc_ck20_DBUS(0),
	     P  => sc_DBUS(0),
	     A  => st_0,
	     CONOF  => st_1,
	     NEN  => st_0,
	     PD => st_0,
	     PEN => st_0,
	     PU => st_1,
	     SONOF => st_0
             );
    sc_DBUS(0) <= DBUS(0); 
 
   -- Input : DBUS(1) pin --	
    i_PAD_DBUS_1 : PLBI8N
    port map(
      	     D  => sc_ck20_DBUS(1),
	     P  => sc_DBUS(1),
	     A  => st_0,
	     CONOF  => st_1,
	     NEN  => st_0,
	     PD => st_0,
	     PEN => st_0,
	     PU => st_1,
	     SONOF => st_0
             );
    sc_DBUS(1) <= DBUS(1); 
    
   -- Input : DBUS(2) pin --	
    i_PAD_DBUS_2 : PLBI8N
    port map(
      	     D  => sc_ck20_DBUS(2),
	     P  => sc_DBUS(2),
	     A  => st_0,
	     CONOF  => st_1,
	     NEN  => st_0,
	     PD => st_0,
	     PEN => st_0,
	     PU => st_1,
	     SONOF => st_0
             );
    sc_DBUS(2) <= DBUS(2); 
 
   -- Input : DBUS(3) pin --	
    i_PAD_DBUS_3 : PLBI8N
    port map(
      	     D  => sc_ck20_DBUS(3),
	     P  => sc_DBUS(3),
	     A  => st_0,
	     CONOF  => st_1,
	     NEN  => st_0,
	     PD => st_0,
	     PEN => st_0,
	     PU => st_1,
	     SONOF => st_0
             );
    sc_DBUS(3) <= DBUS(3);     
    
   -- Input : DBUS(4) pin --	
    i_PAD_DBUS_4 : PLBI8N
    port map(
      	     D  => sc_ck20_DBUS(4),
	     P  => sc_DBUS(4),
	     A  => st_0,
	     CONOF  => st_1,
	     NEN  => st_0,
	     PD => st_0,
	     PEN => st_0,
	     PU => st_1,
	     SONOF => st_0
             );
    sc_DBUS(4) <= DBUS(4); 
 
   -- Input : DBUS(5) pin --	
    i_PAD_DBUS_5 : PLBI8N
    port map(
      	     D  => sc_ck20_DBUS(5),
	     P  => sc_DBUS(5),
	     A  => st_0,
	     CONOF  => st_1,
	     NEN  => st_0,
	     PD => st_0,
	     PEN => st_0,
	     PU => st_1,
	     SONOF => st_0
             );
    sc_DBUS(5) <= DBUS(5); 
    
   -- Input : DBUS(6) pin --	
    i_PAD_DBUS_6 : PLBI8N
    port map(
      	     D  => sc_ck20_DBUS(6),
	     P  => sc_DBUS(6),
	     A  => st_0,
	     CONOF  => st_1,
	     NEN  => st_0,
	     PD => st_0,
	     PEN => st_0,
	     PU => st_1,
	     SONOF => st_0
             );
    sc_DBUS(6) <= DBUS(6); 
 
   -- Input : DBUS(7) pin --	
    i_PAD_DBUS_7 : PLBI8N
    port map(
      	     D  => sc_ck20_DBUS(7),
	     P  => sc_DBUS(7),
	     A  => st_0,
	     CONOF  => st_1,
	     NEN  => st_0,
	     PD => st_0,
	     PEN => st_0,
	     PU => st_1,
	     SONOF => st_0
             );
    sc_DBUS(7) <= DBUS(7);      
    
    
    -- Input : RST pin --	
    i_PAD_RST : PLBI8N
    port map(
      	     D  => sc_ck20_RST,
	     P  => sc_RST,
	     A  => st_0,
	     CONOF  => st_1,
	     NEN  => st_0,
	     PD => st_0,
	     PEN => st_0,
	     PU => st_1,
	     SONOF => st_0
             );
    sc_RST <= RST; 
 
   -- Input : ALE pin --	
    i_PAD_ALE : PLBI8N
    port map(
      	     D  => sc_ck20_ALE,
	     P  => sc_ALE,
	     A  => st_0,
	     CONOF  => st_1,
	     NEN  => st_0,
	     PD => st_0,
	     PEN => st_0,
	     PU => st_1,
	     SONOF => st_0
             );
    sc_ALE <= ALE; 
    
   -- Input : WR pin --	
    i_PAD_WR : PLBI8N
    port map(
      	     D  => sc_ck20_WR,
	     P  => sc_WR,
	     A  => st_0,
	     CONOF  => st_1,
	     NEN  => st_0,
	     PD => st_0,
	     PEN => st_0,
	     PU => st_1,
	     SONOF => st_0
             );
    sc_WR <= WR; 
 
   -- Input : CS(0) pin --	
    i_PAD_CS_0 : PLBI8N
    port map(
      	     D  => sc_ck20_CS(0),
	     P  => sc_CS(0),
	     A  => st_0,
	     CONOF  => st_1,
	     NEN  => st_0,
	     PD => st_0,
	     PEN => st_0,
	     PU => st_1,
	     SONOF => st_0
             );
    sc_CS(0) <= CS(0);     

   -- Input : CS(1) pin --	
    i_PAD_CS_1 : PLBI8N
    port map(
      	     D  => sc_ck20_CS(1),
	     P  => sc_CS(1),
	     A  => st_0,
	     CONOF  => st_1,
	     NEN  => st_0,
	     PD => st_0,
	     PEN => st_0,
	     PU => st_1,
	     SONOF => st_0
             );
    sc_CS(1) <= CS(1);     


   -- Input : CLK pin --	
    i_PAD_CLK : PLBI8N
    port map(
      	     D  => sc_ck20_CLK,
	     P  => sc_CLK,
	     A  => st_0,
	     CONOF  => st_1,
	     NEN  => st_0,
	     PD => st_0,
	     PEN => st_0,
	     PU => st_1,
	     SONOF => st_0
             );
    sc_CLK <= CLK; 



    
  -- Output : H1(0) pin --
    i_PAD_H1_0 : PLBI8N
    port map(
      	     --D  => temp,
	     P  => sc_H1(0),
	     A  => sc_ck20_H1(0),
	     CONOF  => st_0,
	     NEN  => st_1,
	     PD => st_0,
	     PEN => st_1,
	     PU => st_1,
	     SONOF => st_0
             );
    H1(0) <= sc_H1(0);     
    
    
  -- Output : H1(1) pin --
    i_PAD_H1_1 : PLBI8N 
    port map(
      	   --D  => st_0,
	     P  => sc_H1(1),
	     A  => sc_ck20_H1(1),
	     CONOF  => st_0,
	     NEN  => st_1,
	     PD => st_0,
	     PEN => st_1,
	     PU => st_1,
	     SONOF => st_0
             );
    H1(1) <= sc_H1(1);     

  -- Output : H0(0) pin --
    i_PAD_H0_0 : PLBI8N 
    port map(
      	   --D  => sc_null_WR_n,
	     P  => sc_H0(0),
	     A  => sc_ck20_H0(0),
	     CONOF  => st_0,
	     NEN  => st_1,
	     PD => st_0,
	     PEN => st_1,
	     PU => st_1,
	     SONOF => st_0
             );
    H0(0) <= sc_H0(0);     
    
    
  -- Output : H0(1) pin --
    i_PAD_H0_1 : PLBI8N 
    port map(
      	   --D  => sc_null_WR_n,
	     P  => sc_H0(1),
	     A  => sc_ck20_H0(1),
	     CONOF  => st_0,
	     NEN  => st_1,
	     PD => st_0,
	     PEN => st_1,
	     PU => st_1,
	     SONOF => st_0
             );
    H0(1) <= sc_H0(1);  

  -- Output : H0(2) pin --
    i_PAD_H0_2 : PLBI8N 
    port map(
      	   --D  => sc_null_WR_n,
	     P  => sc_H0(2),
	     A  => sc_ck20_H0(2),
	     CONOF  => st_0,
	     NEN  => st_1,
	     PD => st_0,
	     PEN => st_1,
	     PU => st_1,
	     SONOF => st_0
             );
    H0(2) <= sc_H0(2);  

  -- Output : H0(3) pin --
    i_PAD_H0_3 : PLBI8N 
    port map(
      	   --D  => sc_null_WR_n,
	     P  => sc_H0(3),
	     A  => sc_ck20_H0(3),
	     CONOF  => st_0,
	     NEN  => st_1,
	     PD => st_0,
	     PEN => st_1,
	     PU => st_1,
	     SONOF => st_0
             );
    H0(3) <= sc_H0(3);  


  -- Output : SEC pin --
    i_PAD_SEC : PLBI8N 
    port map(
      	   --D  => sc_null_WR_n,
	     P  => sc_SEC,
	     A  => sc_ck20_SEC,
	     CONOF  => st_0,
	     NEN  => st_1,
	     PD => st_0,
	     PEN => st_1,
	     PU => st_1,
	     SONOF => st_0
             );
    SEC <= sc_SEC; 


  -- Output : MIN1(0) pin --
    i_PAD_MIN1_0 : PLBI8N 
    port map(
      	   --D  => sc_null_WR_n,
	     P  => sc_MIN1(0),
	     A  => sc_ck20_MIN1(0),
	     CONOF  => st_0,
	     NEN  => st_1,
	     PD => st_0,
	     PEN => st_1,
	     PU => st_1,
	     SONOF => st_0
             );
    MIN1(0) <= sc_MIN1(0);     
 
 
   -- Output : MIN1(1) pin --
    i_PAD_MIN1_1 : PLBI8N 
    port map(
      	   --D  => sc_null_WR_n,
	     P  => sc_MIN1(1),
	     A  => sc_ck20_MIN1(1),
	     CONOF  => st_0,
	     NEN  => st_1,
	     PD => st_0,
	     PEN => st_1,
	     PU => st_1,
	     SONOF => st_0
             );
    MIN1(1) <= sc_MIN1(1);
 
 
    -- Output : MIN1(2) pin --
    i_PAD_MIN1_2 : PLBI8N 
    port map(
      	   --D  => sc_null_WR_n,
	     P  => sc_MIN1(2),
	     A  => sc_ck20_MIN1(2),
	     CONOF  => st_0,
	     NEN  => st_1,
	     PD => st_0,
	     PEN => st_1,
	     PU => st_1,
	     SONOF => st_0
             );
    MIN1(2) <= sc_MIN1(2);
 
 
  -- Output : MIN0(0) pin --
    i_PAD_MIN0_0 : PLBI8N 
    port map(
      	   --D  => sc_null_WR_n,
	     P  => sc_MIN0(0),
	     A  => sc_ck20_MIN0(0),
	     CONOF  => st_0,
	     NEN  => st_1,
	     PD => st_0,
	     PEN => st_1,
	     PU => st_1,
	     SONOF => st_0
             );
    MIN0(0) <= sc_MIN0(0);     
 
 
   -- Output : MIN0(1) pin --
    i_PAD_MIN0_1 : PLBI8N 
    port map(
      	   --D  => sc_null_WR_n,
	     P  => sc_MIN0(1),
	     A  => sc_ck20_MIN0(1),
	     CONOF  => st_0,
	     NEN  => st_1,
	     PD => st_0,
	     PEN => st_1,
	     PU => st_1,
	     SONOF => st_0
             );
    MIN0(1) <= sc_MIN0(1);
 
 
    -- Output : MIN0(2) pin --
    i_PAD_MIN0_2 : PLBI8N 
    port map(
      	   --D  => sc_null_WR_n,
	     P  => sc_MIN0(2),
	     A  => sc_ck20_MIN0(2),
	     CONOF  => st_0,
	     NEN  => st_1,
	     PD => st_0,
	     PEN => st_1,
	     PU => st_1,
	     SONOF => st_0
             );
    MIN0(2) <= sc_MIN0(2); 
 
 
     -- Output : MIN0(3) pin --
    i_PAD_MIN0_3 : PLBI8N 
    port map(
      	   --D  => sc_null_WR_n,
	     P  => sc_MIN0(3),
	     A  => sc_ck20_MIN0(3),
	     CONOF  => st_0,
	     NEN  => st_1,
	     PD => st_0,
	     PEN => st_1,
	     PU => st_1,
	     SONOF => st_0
             );
    MIN0(3) <= sc_MIN0(3); 

end struc;