ck20_top_old.vhd

计数时钟芯片代码

library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all; 
use IEEE.std_logic_unsigned.all; 


entity ck20_top is
  port  (
         DBUS_top : in std_logic_vector(7 downto 0);
         RST_top  : in std_logic;
	 ALE_top  : in std_logic;
         WR_top   : in std_logic;
	 CS_top   : in std_logic_vector(1 downto 0);
	 CLK_top  : in std_logic;
	 H1_top   : out std_logic_vector(1 downto 0);
	 H0_top   : out std_logic_vector(3 downto 0);
	 SEC_top  : out std_logic;
	 MIN1_top : out std_logic_vector(2 downto 0);
	 MIN0_top : out std_logic_vector(3 downto 0)
         );
end ck20_top;
         
architecture struc of ck20_top is
	Signal	DBUS_sc: std_logic_vector(7 downto 0);
	Signal  RST_sc : std_logic;
	Signal  ALE_sc : std_logic;
	Signal	WR_sc  : std_logic;
	Signal	CS_sc  : std_logic_vector(1 downto 0);
	Signal	CLK_sc : std_logic;
	Signal	H1_sc  : std_logic_vector(1 downto 0);
	Signal	H0_sc  : std_logic_vector(3 downto 0);
	Signal	SEC_sc : std_logic;
	Signal	MIN1_sc: std_logic_vector(2 downto 0);
	Signal	MIN0_sc: std_logic_vector(3 downto 0);
	Signal  st_0   : std_logic;
	Signal  st_1   : std_logic;

 component ck20
    port ( 
      DBUS 	: in std_logic_vector(7 downto 0);
      RST 	: in std_logic;
      ALE 	: in std_logic;
      WR 	: in std_logic;
      CS 	: in std_logic_vector(1 downto 0);
      CLK 	: in std_logic;
      H1  	: out std_logic_vector(1 downto 0);
      H0  	: out std_logic_vector(3 downto 0);
      SEC 	: out std_logic;
      MIN1	: out std_logic_vector(2 downto 0);
      MIN0	: out std_logic_vector(3 downto 0)
		 );
end component;

	
  -- PAD for normal I
  component XMD
   port(
      O		:	out   STD_ULOGIC;
      I		:	in    STD_ULOGIC;
      PU	:	in    STD_ULOGIC;
      PD	:	in    STD_ULOGIC;
      SMT	:	in    STD_ULOGIC);
end component;

  -- PAD for normal O
  component YA2GSD
   port(
      O		:	out   STD_ULOGIC;
      I		:	in    STD_ULOGIC;
      E		:	in    STD_ULOGIC;
      E2	:	in    STD_ULOGIC;
      E4	:	in    STD_ULOGIC;
      E8	:	in    STD_ULOGIC;
      SR        :       in    STD_ULOGIC);
end component;
   
  -- PAD for OSCillator
--    component UROSCHINTD
--  port(
--  O		:	out   STD_ULOGIC;
--I		:	in    STD_ULOGIC;
--      IO	:	inout STD_ULOGIC;
--      E		:	in    STD_ULOGIC;
--      EB	:	in    STD_ULOGIC;
--      S0	:	in    STD_ULOGIC;
--      S1	:	in    STD_ULOGIC;
--      FEB	:	in    STD_ULOGIC);
--  end component;
    
begin                
  inst_ck20 :ck20
  port map(
  	DBUS		=> DBUS_sc,
  	RST		=> RST_sc,
  	ALE		=> ALE_sc,
  	WR		=> WR_sc,
  	CS		=> CS_sc,
  	CLK		=> CLK_sc,
  	H1		=> H1_sc,
  	H0		=> H0_sc,
  	SEC		=> SEC_sc,
  	MIN1		=> MIN1_sc,
  	MIN0		=> MIN0_sc
  	);

  -- Constant '1' and '0' define
  st_0 <= '0';
  st_1 <= '1';  


  -- Input : RST pin --
    i_PAD_RST : XMD 
    port map(
      	O  		=> RST_sc,
	I 		=> RST_top,
        PU		=> st_0,
        PD		=> st_0,
        SMT		=> st_0
   );

  -- Input : ALE pin --
    i_PAD_ALE : XMD 
    port map(
      	O  		=> ALE_sc,
	I 		=> ALE_top,
        PU		=> st_0,
        PD		=> st_0,
        SMT		=> st_0
   );
   
  -- Input : WR pin --
    i_PAD_WR : XMD 
    port map(
      	O  		=> WR_sc,
	I 		=> WR_top,
        PU		=> st_0,
        PD		=> st_0,
        SMT		=> st_0
   );
   
  -- Input : CS(0) pin --
    i_PAD_CS_0 : XMD 
    port map(
      	O  		=> CS_sc(0),
	I 		=> CS_top(0),
        PU		=> st_0,
        PD		=> st_0,
        SMT		=> st_0
   );
   
  -- Input : CS(1) pin --
    i_PAD_CS_1 : XMD 
    port map(
      	O  		=> CS_sc(1),
	I 		=> CS_top(1),
        PU		=> st_0,
        PD		=> st_0,
        SMT		=> st_0
   );
   
  -- Input : DBUS(0) pin --
    i_PAD_DBUS_0 : XMD 
    port map(
      	O  		=> DBUS_sc(0),
	I 		=> DBUS_top(0),
        PU		=> st_0,
        PD		=> st_0,
        SMT		=> st_0
   ); 
   
     -- Input : DBUS(1) pin --
    i_PAD_DBUS_1 : XMD 
    port map(
      	O  		=> DBUS_sc(1),
	I 		=> DBUS_top(1),
        PU		=> st_0,
        PD		=> st_0,
        SMT		=> st_0
   );   
   
     -- Input : DBUS(2) pin --
    i_PAD_DBUS_2 : XMD 
    port map(
      	O  		=> DBUS_sc(2),
	I 		=> DBUS_top(2),
        PU		=> st_0,
        PD		=> st_0,
        SMT		=> st_0
   );   
   
     -- Input : DBUS(3) pin --
    i_PAD_DBUS_3 : XMD 
    port map(
      	O  		=> DBUS_sc(3),
	I 		=> DBUS_top(3),
        PU		=> st_0,
        PD		=> st_0,
        SMT		=> st_0
   );   
   
     -- Input : DBUS(4) pin --
    i_PAD_DBUS_4 : XMD 
    port map(
      	O  		=> DBUS_sc(4),
	I 		=> DBUS_top(4),
        PU		=> st_0,
        PD		=> st_0,
        SMT		=> st_0
   );   
   
     -- Input : DBUS(5) pin --
    i_PAD_DBUS_5 : XMD 
    port map(
      	O  		=> DBUS_sc(5),
	I 		=> DBUS_top(5),
        PU		=> st_0,
        PD		=> st_0,
        SMT		=> st_0
   );   
   
     -- Input : DBUS(6) pin --
    i_PAD_DBUS_6 : XMD 
    port map(
      	O  		=> DBUS_sc(6),
	I 		=> DBUS_top(6),
        PU		=> st_0,
        PD		=> st_0,
        SMT		=> st_0
   );   
   
     -- Input : DBUS(7) pin --
    i_PAD_DBUS_7 : XMD 
    port map(
      	O  		=> DBUS_sc(7),
	I 		=> DBUS_top(7),
        PU		=> st_0,
        PD		=> st_0,
        SMT		=> st_0
   ); 
   
   
    -- Output : H1(0) pin --
    i_PAD_H1_0 : YA2GSD 
    port map(
	O  		=> H1_top(0),
	I  		=> H1_sc(0),
	E		=> st_1,
        E2		=> st_1,
        E4		=> st_1,
        E8		=> st_0,
        SR    		=> st_1
   );

    -- Output : H1(1) pin --
    i_PAD_H1_1 : YA2GSD 
    port map(
	O  		=> H1_top(1),
	I  		=> H1_sc(1),
	E		=> st_1,
        E2		=> st_1,
        E4		=> st_1,
        E8		=> st_0,
        SR    		=> st_1
   );

    -- Output : H0(0) pin --
    i_PAD_H0_0 : YA2GSD 
    port map(
	O  		=> H0_top(0),
	I  		=> H0_sc(0),
	E		=> st_1,
        E2		=> st_1,
        E4		=> st_1,
        E8		=> st_0,
        SR    		=> st_1
   );

    -- Output : H0(1) pin --
    i_PAD_H0_1 : YA2GSD 
    port map(
	O  		=> H0_top(1),
	I  		=> H0_sc(1),
	E		=> st_1,
        E2		=> st_1,
        E4		=> st_1,
        E8		=> st_0,
        SR    		=> st_1
   );

    -- Output : H0(2) pin --
    i_PAD_H0_2 : YA2GSD 
    port map(
	O  		=> H0_top(2),
	I  		=> H0_sc(2),
	E		=> st_1,
        E2		=> st_1,
        E4		=> st_1,
        E8		=> st_0,
        SR    		=> st_1
   );

    -- Output : H0(3) pin --
    i_PAD_H0_3 : YA2GSD 
    port map(
	O  		=> H0_top(3),
	I  		=> H0_sc(3),
	E		=> st_1,
        E2		=> st_1,
        E4		=> st_1,
        E8		=> st_0,
        SR    		=> st_1
   );


    -- Output : MIN0(0) pin --
    i_PAD_MIN0_0 : YA2GSD 
    port map(
	O  		=> MIN0_top(0),
	I  		=> MIN0_sc(0),
	E		=> st_1,
        E2		=> st_1,
        E4		=> st_1,
        E8		=> st_0,
        SR    		=> st_1
   );

    -- Output : MIN0(1) pin --
    i_PAD_MIN0_1 : YA2GSD 
    port map(
	O  		=> MIN0_top(1),
	I  		=> MIN0_sc(1),
	E		=> st_1,
        E2		=> st_1,
        E4		=> st_1,
        E8		=> st_0,
        SR    		=> st_1
   );

    -- Output : MIN0(2) pin --
    i_PAD_MIN0_2 : YA2GSD 
    port map(
	O  		=> MIN0_top(2),
	I  		=> MIN0_sc(2),
	E		=> st_1,
        E2		=> st_1,
        E4		=> st_1,
        E8		=> st_0,
        SR    		=> st_1
   );

    -- Output : MIN0(3) pin --
    i_PAD_MIN0_3 : YA2GSD 
    port map(
	O  		=> MIN0_top(3),
	I  		=> MIN0_sc(3),
	E		=> st_1,
        E2		=> st_1,
        E4		=> st_1,
        E8		=> st_0,
        SR    		=> st_1
   );
   
   
    -- Output : MIN1(0) pin --
    i_PAD_MIN1_0 : YA2GSD 
    port map(
	O  		=> MIN1_top(0),
	I  		=> MIN1_sc(0),
	E		=> st_1,
        E2		=> st_1,
        E4		=> st_1,
        E8		=> st_0,
        SR    		=> st_1
   );

    -- Output : MIN1(1) pin --
    i_PAD_MIN1_1 : YA2GSD 
    port map(
	O  		=> MIN1_top(1),
	I  		=> MIN1_sc(1),
	E		=> st_1,
        E2		=> st_1,
        E4		=> st_1,
        E8		=> st_0,
        SR    		=> st_1
   );

    -- Output : MIN1(2) pin --
    i_PAD_MIN1_2 : YA2GSD 
    port map(
	O  		=> MIN1_top(2),
	I  		=> MIN1_sc(2),
	E		=> st_1,
        E2		=> st_1,
        E4		=> st_1,
        E8		=> st_0,
        SR    		=> st_1
   );

     -- Output : SEC pin --
    i_PAD_SEC : YA2GSD 
    port map(
	O  		=> SEC_top,
	I  		=> SEC_sc,
	E		=> st_1,
        E2		=> st_1,
        E4		=> st_1,
        E8		=> st_0,
        SR    		=> st_1
   );

   -- PAD for OSCillator --
   i_PAD_CLK : XMD
     port map(
         O 		=> CLK_sc,
	 I 		=> CLK_top,
         PU		=> st_0,
         PD		=> st_0,
         SMT		=> st_0
   );
end struc;