spim.tex

Spim软件的一些源码。其中有Xspim的

\pinstX{ror Rdest, Rsrc1, Src2}{Rotate Right}
Rotate the contents of register {\tt Rsrc1} left (right) by the
distance indicated by {\tt Src2} and put the result in register
{\tt Rdest}.

\inst{sll Rdest, Rsrc1, Src2}{Shift Left Logical}
\instX{sllv Rdest, Rsrc1, Rsrc2}{Shift Left Logical Variable}
\instX{sra Rdest, Rsrc1, Src2}{Shift Right Arithmetic}
\instX{srav Rdest, Rsrc1, Rsrc2}{Shift Right Arithmetic Variable}
\instX{srl Rdest, Rsrc1, Src2}{Shift Right Logical}
\instX{srlv Rdest, Rsrc1, Rsrc2}{Shift Right Logical Variable}
Shift the contents of register {\tt Rsrc1} left (right) by the
distance indicated by {\tt Src2} ({\tt Rsrc2}) and put the
result in register {\tt Rdest}.

\inst{sub Rdest, Rsrc1, Src2}{Subtract (with overflow)}
\instX{subu Rdest, Rsrc1, Src2}{Subtract (without overflow)}
Put the difference of the integers from register {\tt Rsrc1} and {\tt
Src2} into register {\tt Rdest}.

\inst{xor Rdest, Rsrc1, Src2}{XOR}
\instX{xori Rdest, Rsrc1, Imm}{XOR Immediate}
Put the logical XOR of the integers from register {\tt Rsrc1} and
{\tt Src2} (or {\tt Imm}) into register {\tt Rdest}.


\subsection {Constant-Manipulating Instructions}

\pinst{li Rdest, imm}{Load Immediate}
Move the immediate {\tt imm} into register {\tt Rdest}.

\inst{lui Rdest, imm}{Load Upper Immediate}
Load the lower halfword of the immediate {\tt imm} into the upper
halfword of register {\tt Rdest}.  The lower bits of the register are
set to 0.


\subsection {Comparison Instructions}

In all instructions below, {\tt Src2} can either be a register or an
immediate value (a 16 bit integer).

\pinst{seq Rdest, Rsrc1, Src2}{Set Equal}
Set register {\tt Rdest} to 1 if register {\tt Rsrc1} equals {\tt
Src2} and to be 0 otherwise.

\pinst{sge Rdest, Rsrc1, Src2}{Set Greater Than Equal}
\pinstX{sgeu Rdest, Rsrc1, Src2}{Set Greater Than Equal Unsigned}
Set register {\tt Rdest} to 1 if register {\tt Rsrc1} is greater
than or equal to {\tt Src2} and to 0 otherwise.

\pinst{sgt Rdest, Rsrc1, Src2}{Set Greater Than}
\pinstX{sgtu Rdest, Rsrc1, Src2}{Set Greater Than Unsigned}
Set register {\tt Rdest} to 1 if register {\tt Rsrc1} is greater
than {\tt Src2} and to 0 otherwise.

\pinst{sle Rdest, Rsrc1, Src2}{Set Less Than Equal}
\pinstX{sleu Rdest, Rsrc1, Src2}{Set Less Than Equal Unsigned}
Set register {\tt Rdest} to 1 if register {\tt Rsrc1} is less than
or equal to {\tt Src2} and to 0 otherwise.

\inst{slt Rdest, Rsrc1, Src2}{Set Less Than}
\instX{slti Rdest, Rsrc1, Imm}{Set Less Than Immediate}
\instX{sltu Rdest, Rsrc1, Src2}{Set Less Than Unsigned}
\instX{sltiu Rdest, Rsrc1, Imm}{Set Less Than Unsigned Immediate}
Set register {\tt Rdest} to 1 if register {\tt Rsrc1} is less than
{\tt Src2} (or {\tt Imm}) and to 0 otherwise.

\pinst{sne Rdest, Rsrc1, Src2}{Set Not Equal}
Set register {\tt Rdest} to 1 if register {\tt Rsrc1} is not equal
to {\tt Src2} and to 0 otherwise.


\subsection {Branch and Jump Instructions}

In all instructions below, {\tt Src2} can either be a register or an
immediate value (integer).  Branch instructions use a signed 16-bit
offset field; hence they can jump $2^{15}-1$ {\em instructions\/} (not
bytes) forward or $2^{15}$ instructions backwards.  The {\em jump\/}
instruction contains a 26 bit address field.

\pinst{b label}{Branch instruction}
Unconditionally branch to the instruction at the label.

\inst{bc{\em z}t label}{Branch Coprocessor $z$ True}
\instX{bc{\em z}f label}{Branch Coprocessor $z$ False}
Conditionally branch to the instruction at the label if coprocessor
$z$'s condition flag is true (false).

\inst{beq Rsrc1, Src2, label}{Branch on Equal}
Conditionally branch to the instruction at the label if the contents
of register {\tt Rsrc1} equals {\tt Src2}.

\pinst{beqz Rsrc, label}{Branch on Equal Zero}
Conditionally branch to the instruction at the label if the contents
of {\tt Rsrc} equals 0.

\pinst{bge Rsrc1, Src2, label}{Branch on Greater Than Equal}
\pinstX{bgeu Rsrc1, Src2, label}{Branch on GTE Unsigned}
Conditionally branch to the instruction at the label if the contents
of register {\tt Rsrc1} are greater than or equal to {\tt Src2}.

\inst{bgez Rsrc, label}{Branch on Greater Than Equal Zero}
Conditionally branch to the instruction at the label if the contents
of {\tt Rsrc} are greater than or equal to 0.

\inst{bgezal Rsrc, label}{Branch on Greater Than Equal Zero And Link}
Conditionally branch to the instruction at the label if the contents
of {\tt Rsrc} are greater than or equal to 0. Save the address of
the next instruction in register 31.

\pinst{bgt Rsrc1, Src2, label}{Branch on Greater Than}
\pinstX{bgtu Rsrc1, Src2, label}{Branch on Greater Than Unsigned}
Conditionally branch to the instruction at the label if the contents
of register {\tt Rsrc1} are greater than {\tt Src2}.

\inst{bgtz Rsrc, label}{Branch on Greater Than Zero}
Conditionally branch to the instruction at the label if the contents
of {\tt Rsrc} are greater than 0.

\pinst{ble Rsrc1, Src2, label}{Branch on Less Than Equal}
\pinstX{bleu Rsrc1, Src2, label}{Branch on LTE Unsigned}
Conditionally branch to the instruction at the label if the contents
of register {\tt Rsrc1} are less than or equal to {\tt Src2}.

\inst{blez Rsrc, label}{Branch on Less Than Equal Zero}
Conditionally branch to the instruction at the label if the contents
of {\tt Rsrc} are less than or equal to 0.

\inst{bgezal Rsrc, label}{Branch on Greater Than Equal Zero And Link}
\instX{bltzal Rsrc, label}{Branch on Less Than And Link}
Conditionally branch to the instruction at the label if the contents
of {\tt Rsrc} are greater or equal to 0 or less than 0,
respectively. Save the address of the next instruction in register 31.

\pinst{blt Rsrc1, Src2, label}{Branch on Less Than}
\pinstX{bltu Rsrc1, Src2, label}{Branch on Less Than Unsigned}
Conditionally branch to the instruction at the label if the contents
of register {\tt Rsrc1} are less than {\tt Src2}.

\inst{bltz Rsrc, label}{Branch on Less Than Zero}
Conditionally branch to the instruction at the label if the contents
of {\tt Rsrc} are less than 0.

\inst{bne Rsrc1, Src2, label}{Branch on Not Equal}
Conditionally branch to the instruction at the label if the contents
of register {\tt Rsrc1} are not equal to {\tt Src2}.

\pinst{bnez Rsrc, label}{Branch on Not Equal Zero}
Conditionally branch to the instruction at the label if the contents
of {\tt Rsrc} are not equal to 0.

\inst{j label}{Jump}
Unconditionally jump to the instruction at the label.

\inst{jal label}{Jump and Link}
\instX{jalr Rsrc}{Jump and Link Register}
Unconditionally jump to the instruction at the label or whose address
is in register {\tt Rsrc}.  Save the address of the next
instruction in register 31.

\inst{jr Rsrc}{Jump Register}
Unconditionally jump to the instruction whose address is in register
{\tt Rsrc}.


\subsection {Load Instructions}

\pinst{la Rdest, address}{Load Address}
Load computed {\em address\/}, not the contents of the location, into
register {\tt Rdest}.

\inst{lb Rdest, address}{Load Byte}
\instX{lbu Rdest, address}{Load Unsigned Byte}
Load the byte at {\em address\/} into register {\tt Rdest}.  The byte
is sign-extended by the {\tt lb}, but not the {\tt lbu}, instruction.

\pinst{ld Rdest, address}{Load Double-Word}
Load the 64-bit quantity at {\em address\/} into registers {\tt Rdest}
and {\tt Rdest + 1}.

\inst{lh Rdest, address}{Load Halfword}
\instX{lhu Rdest, address}{Load Unsigned Halfword}
Load the 16-bit quantity (halfword) at {\em address\/} into register
{\tt Rdest}.  The halfword is sign-extended by the {\tt lh}, but not
the {\tt lhu}, instruction

\inst{lw Rdest, address}{Load Word}
Load the 32-bit quantity (word) at {\em address\/} into register {\tt
Rdest}.

\inst{lwc{\em z\/} Rdest, address}{Load Word Coprocessor}
Load the word at {\em address\/} into register {\tt Rdest} of
coprocessor $z$ (0--3).

\inst{lwl Rdest, address}{Load Word Left}
\instX{lwr Rdest, address}{Load Word Right}
Load the left (right) bytes from the word at the possibly-unaligned
{\em address\/} into register {\tt Rdest}.

\pinst{ulh Rdest, address}{Unaligned Load Halfword}
\pinstX{ulhu Rdest, address}{Unaligned Load Halfword Unsigned}
Load the 16-bit quantity (halfword) at the possibly-unaligned {\em
address\/} into register {\tt Rdest}.  The halfword is sign-extended
by the {\tt ulh}, but not the {\tt ulhu}, instruction

\pinst{ulw Rdest, address}{Unaligned Load Word}
Load the 32-bit quantity (word) at the possibly-unaligned {\em
address\/}  into register {\tt Rdest}.


\subsection {Store Instructions}

\inst{sb Rsrc, address}{Store Byte}
Store the low byte from register {\tt Rsrc} at {\em address\/}.

\pinst{sd Rsrc, address}{Store Double-Word}
Store the 64-bit quantity in registers {\tt Rsrc} and {\tt Rsrc
+ 1} at {\em address\/}.

\inst{sh Rsrc, address}{Store Halfword}
Store the low halfword from register {\tt Rsrc} at {\em address\/}.

\inst{sw Rsrc, address}{Store Word}
Store the word from register {\tt Rsrc} at {\em address\/}.

\inst{swc{\em z\/} Rsrc, address}{Store Word Coprocessor}
Store the word from register {\tt Rsrc} of coprocessor $z$ at
{\em address\/}.

\inst{swl Rsrc, address}{Store Word Left}
\instX{swr Rsrc, address}{Store Word Right}
Store the left (right) bytes from register {\tt Rsrc} at the
possibly-unaligned {\em address\/}.

\pinst{ush Rsrc, address}{Unaligned Store Halfword}
Store the low halfword from register {\tt Rsrc} at the
possibly-unaligned {\em address\/}.

\pinst{usw Rsrc, address}{Unaligned Store Word}
Store the word from register {\tt Rsrc} at the possibly-unaligned
{\em address\/}.


\subsection{Data Movement Instructions}

\pinst{move Rdest, Rsrc}{Move}
Move the contents of {\tt Rsrc} to {\tt Rdest}.

\bigskip

The multiply and divide unit produces its result in two additional
registers, hi and lo.  These instructions move values to and from
these registers.  The multiply, divide, and remainder instructions
described above are pseudoinstructions that make it appear as if this
unit operates on the general registers and detect error conditions
such as divide by zero or overflow.

\inst{mfhi Rdest}{Move From hi}
\instX{mflo Rdest}{Move From lo}
Move the contents of the hi (lo) register to register {\tt Rdest}.

\inst{mthi Rdest}{Move To hi}
\instX{mtlo Rdest}{Move To lo}
Move the contents register {\tt Rdest} to the hi (lo) register.

\bigskip

Coprocessors have their own register sets.  These instructions move
values between these registers and the CPU's registers.

\inst{mfc{\em z\/} Rdest, CPsrc}{Move From Coprocessor $z$}
Move the contents of coprocessor $z$'s register {\tt CPsrc} to CPU
register {\tt Rdest}.

\pinst{mfc1.d Rdest, FRsrc1}{Move Double From Coprocessor 1}
Move the contents of floating point registers {\tt FRsrc1} and
{\tt FRsrc1 + 1} to CPU registers {\tt Rdest} and {\tt Rdest + 1}.

\inst{mtc{\em z\/} Rsrc, CPdest}{Move To Coprocessor $z$}
Move the contents of CPU register {\tt Rsrc} to coprocessor $z$'s
register {\tt CPdest}.


\subsection{Floating Point Instructions}

The MIPS has a floating point coprocessor (numbered 1) that operates
on single precision (32-bit) and double precision (64-bit) floating
point numbers.  This coprocessor has its own registers, which are
numbered {\tt \$f0}--{\tt \$f31}.  Because these registers are only
32-bits wide, two of them are required to hold doubles. To simplify
matters, floating point operations only use even-numbered
registers---including instructions that operate on single floats.

Values are moved in or out of these registers a word (32-bits) at a
time by {\tt lwc1}, {\tt swc1}, {\tt mtc1}, and {\tt mfc1}
instructions described above or by the {\tt l.s}, {\tt l.d}, {\tt
s.s}, and {\tt s.d} pseudoinstructions described below.  The flag set
by floating point comparison operations is read by the CPU with its