spim.tex

Spim软件的一些源码。其中有Xspim的

  \small
  \begin{center}
  \begin{tabular}{|l|r|l|}
    \hline
     {\bf Register Name} & {\bf Number} & \multicolumn{1}{|c|}{\bf Usage} \\
     \hline
     \hline
      zero & 0 & Constant 0 \\
      at & 1 & Reserved for assembler \\
      v0 & 2 & Expression evaluation and \\
      v1 & 3 & \ \ \ \ results of a function \\
      a0 & 4 & Argument 1 \\
      a1 & 5 & Argument 2 \\
      a2 & 6 & Argument 3 \\
      a3 & 7 & Argument 4 \\
      t0 & 8 & Temporary (not preserved across call) \\
      t1 & 9 & Temporary (not preserved across call) \\
      t2 & 10 & Temporary (not preserved across call) \\
      t3 & 11 & Temporary (not preserved across call) \\
      t4 & 12 & Temporary (not preserved across call) \\
      t5 & 13 & Temporary (not preserved across call) \\
      t6 & 14 & Temporary (not preserved across call) \\
      t7 & 15 & Temporary (not preserved across call) \\
      s0 & 16 & Saved temporary (preserved across call) \\
      s1 & 17 & Saved temporary (preserved across call) \\
      s2 & 18 & Saved temporary (preserved across call) \\
      s3 & 19 & Saved temporary (preserved across call) \\
      s4 & 20 & Saved temporary (preserved across call) \\
      s5 & 21 & Saved temporary (preserved across call) \\
      s6 & 22 & Saved temporary (preserved across call) \\
      s7 & 23 & Saved temporary (preserved across call) \\
      t8 & 24 & Temporary (not preserved across call) \\
      t9 & 25 & Temporary (not preserved across call) \\
      k0 & 26 & Reserved for OS kernel \\
      k1 & 27 & Reserved for OS kernel \\
      gp & 28 & Pointer to global area \\
      sp & 29 & Stack pointer \\
      fp or s8 & 30 & Frame pointer \\
      ra & 31 & Return address (used by function call) \\
     \hline
  \end{tabular}
  \end{center}
  \caption{MIPS registers and the convention governing their use.}
  \label{tab:reg}
\end{table}

The MIPS (and SPIM) central processing unit contains 32 general
purpose 32-bit registers that are numbered 0--31.  Register $n$ is designated
by {\tt \$n}.  Register {\tt \$0} always contains the hardwired value
0.  MIPS has established a set of conventions as to how registers
should be used.  These suggestions are guidelines, which are not
enforced by the hardware.  However a program that violates them will
not work properly with other software.  Table~\ref{tab:reg} lists the
registers and describes their intended use.

Registers {\tt \$at} (1), {\tt \$k0} (26), and {\tt \$k1} (27) are
reserved for use by the assembler and operating system.

Registers {\tt \$a0}--{\tt \$a3} (4--7) are used to pass the first
four arguments to routines (remaining arguments are passed on the
stack).  Registers {\tt \$v0} and {\tt \$v1} (2, 3) are used to return
values from functions.  Registers {\tt \$t0}--{\tt \$t9} (8--15, 24,
25) are caller-saved registers used for temporary quantities that do
not need to be preserved across calls.  Registers {\tt \$s0}--{\tt
\$s7} (16--23) are callee-saved registers that hold long-lived values
that should be preserved across calls.

Register {\tt \$sp} (29) is the stack pointer, which points to the last
location in use on the stack.\footnote{In earlier version of SPIM, {\tt
\$sp} was documented as pointing at the first free word on the stack (not
the last word of the stack frame).  Recent MIPS documents have made it clear
that this was an error.  Both conventions work equally well, but we choose
to follow the real system.}  Register {\tt \$fp} (30) is the frame
pointer.\footnote{The MIPS compiler does not use a frame pointer, so this
register is used as callee-saved register {\tt \$s8}.} Register {\tt \$ra}
(31) is written with the return address for a call by the {\tt jal}
instruction.

Register {\tt \$gp} (28) is a global pointer that points into the
middle of a 64K block of memory in the heap that holds constants and
global variables.  The objects in this heap can be quickly accessed
with a single load or store instruction.

In addition, coprocessor 0 contains registers that are useful to
handle exceptions.  SPIM does not implement all of these registers,
since they are not of much use in a simulator or are part of the
memory system, which is not implemented.  However, it does provide the
following:
\begin{center}
  \small
  \begin{tabular}{|l|c|l|}
    \hline
    {\bf Register Name} & {\bf Number} & \multicolumn{1}{|c|}{\bf Usage} \\
    \hline
    \hline
    BadVAddr & 8 & Memory address at which address exception occurred \\
    Status & 12 & Interrupt mask and enable bits \\
    Cause & 13 & Exception type and pending interrupt bits \\
    EPC & 14 & Address of instruction that caused exception \\
    \hline
  \end{tabular}
\end{center}
These registers are part of coprocessor 0's register set and are
accessed by the {\tt lwc0}, {\tt mfc0}, {\tt mtc0}, and {\tt swc0}
instructions.

\begin{figure}
  \centerline{\psfig{figure=status_reg.id}}
  \caption{The {\tt Status} register.}
  \label{fig:status_reg}
\end{figure}
\begin{figure}
  \centerline{\psfig{figure=cause_reg.id}}
  \caption{The {\tt Cause} register.}
  \label{fig:cause_reg}
\end{figure}
Figure~\ref{fig:status_reg} describes the bits in the {\tt Status}
register that are implemented by SPIM.  The {\tt interrupt mask}
contains a bit for each of the eight interrupt levels.  If a bit is
one, interrupts at that level are allowed.  If the bit is zero,
interrupts at that level are disabled.  The low six bits of the {\tt
Status} register implement a three-level stack for the {\tt
kernel/user} and {\tt interrupt enable} bits.  The {\tt kernel/user}
bit is 0 if the program was running in the kernel when the interrupt
occurred and 1 if it was in user mode. If the {\tt interrupt enable}
bit is 1, interrupts are allowed.  If it is 0, they are disabled. At an
interrupt, these six bits are shifted left by two bits, so the current
bits become the previous bits and the previous bits become the old
bits.  The current bits are both set to 0 (i.e., kernel mode with
interrupts disabled).

Figure~\ref{fig:cause_reg} describes the bits in the {\tt Cause}
register.  The eight {\tt pending interrupt} bits correspond to the
eight interrupt levels.  A bit becomes 1 when an interrupt at its level
has occurred but has not been serviced.  The {\tt exception code}
bits contain a code from the following table describing the cause
of an exception.
\begin{center}
  \small
  \begin{tabular}{|l|l|l|}
    \hline
    {\bf Number} & {\bf Name} & {\bf Description} \\
    \hline
    \hline
    0 & INT & External interrupt \\
    4 & ADDRL & Address error exception (load or instruction fetch) \\
    5 & ADDRS & Address error exception (store) \\
    6 & IBUS & Bus error on instruction fetch \\
    7 & DBUS & Bus error on data load or store \\
    8 & SYSCALL & Syscall exception \\
    9 & BKPT & Breakpoint exception \\
    10&  RI & Reserved instruction exception \\
    12&  OVF & Arithmetic overflow exception \\
    \hline
  \end{tabular}
\end{center}

\subsection{Byte Order}

Processors can number the bytes within a word to make the byte with
the lowest number either the leftmost or rightmost one.  The convention
used by a machine is its {\em byte order\/}.  MIPS processors can
operate with either {\em big-endian\/} byte order:
\begin{center}
  \begin{tabular}{|c|c|c|c|}
    \multicolumn{4}{c}{{\bf Byte \#}} \\
    \hline
    0 & 1 & 2 & 3 \\
    \hline
  \end{tabular}
\end{center}
or {\em little-endian\/} byte order:
\begin{center}
  \begin{tabular}{|c|c|c|c|}
    \multicolumn{4}{c}{{\bf Byte \#}} \\
    \hline
    3 & 2 & 1 & 0 \\
    \hline
  \end{tabular}
\end{center}
SPIM operates with both byte orders.  SPIM's byte order is determined
by the byte order of the underlying hardware running the simulator.
On a DECstation 3100, SPIM is little-endian, while on a HP Bobcat, Sun
4 or PC/RT, SPIM is big-endian.

\subsection {Addressing Modes}

MIPS is a load/store architecture, which means that only load and
store instructions access memory.  Computation instructions operate
only on values in registers.  The bare machine provides only one
memory addressing mode: {\tt c(rx)}, which uses the sum of the
immediate (integer) {\tt c} and the contents of register {\tt rx} as
the address.  The virtual machine provides the following addressing
modes for load and store instructions:
\begin{center}
  \small
  \begin{tabular}{|l|l|}
    \hline
    \multicolumn{1}{|c|}{\bf Format} &
	\multicolumn{1}{|c|}{\bf Address Computation} \\
    \hline
    \hline
    (register) &  contents of register \\
    imm & immediate \\
    imm (register) & immediate + contents of register \\
    symbol & address of symbol \\
    symbol $\pm$ imm & address of symbol $+$ or $-$ immediate \\
    symbol (register) & address of symbol + contents of register \\
    symbol $\pm$ imm (register) & (address of symbol $+$ or $-$ immediate) + contents of register \\
    \hline
  \end{tabular}
\end{center}

Most load and store instructions operate only on aligned data.  A
quantity is {\em aligned\/} if its memory address is a multiple of its
size in bytes.  Therefore, a halfword object must be stored at even
addresses and a full word object must be stored at addresses that are
a multiple of 4.  However, MIPS provides some instructions for
manipulating unaligned data.

\subsection {Arithmetic and Logical Instructions}

In all instructions below, {\tt Src2} can either be a register or an
immediate value (a 16 bit integer). The immediate forms of the
instructions are only included for reference.  The assembler will
translate the more general form of an instruction (e.g., {\tt add})
into the immediate form (e.g., {\tt addi}) if the second argument is
constant.

\pinst{abs Rdest, Rsrc}{Absolute Value}
Put the absolute value of the integer from register {\tt Rsrc} in
register {\tt Rdest}.

\inst{add Rdest, Rsrc1, Src2}{Addition (with overflow)}
\instX{addi Rdest, Rsrc1, Imm}{Addition Immediate (with overflow)}
\instX{addu Rdest, Rsrc1, Src2}{Addition (without overflow)}
\instX{addiu Rdest, Rsrc1, Imm}{Addition Immediate (without overflow)}
Put the sum of the integers from register {\tt Rsrc1} and {\tt
Src2} (or {\tt Imm}) into register {\tt Rdest}.

\inst{and Rdest, Rsrc1, Src2}{AND}
\instX{andi Rdest, Rsrc1, Imm}{AND Immediate}
Put the logical AND of the integers from register {\tt Rsrc1} and
{\tt Src2} (or {\tt Imm}) into register {\tt Rdest}.

\inst{div Rsrc1, Rsrc2}{Divide (signed)}
\instX{divu Rsrc1, Rsrc2}{Divide (unsigned)}
Divide the contents of the two registers.
{\tt divu} treats is operands as unsigned values.  Leave the quotient in
register {\tt lo} and the remainder in register {\tt hi}.  Note that
if an operand is negative, the remainder is unspecified by the MIPS
architecture and depends on the conventions of the machine on which
SPIM is run.

\pinst{div Rdest, Rsrc1, Src2}{Divide (signed, with overflow)}
\pinstX{divu Rdest, Rsrc1, Src2}{Divide (unsigned, without overflow)}
Put the quotient of the integers from register {\tt Rsrc1} and {\tt
Src2} into register {\tt Rdest}. {\tt divu} treats is operands as
unsigned values.

\pinst{mul Rdest, Rsrc1, Src2}{Multiply (without overflow)}
\pinst{mulo Rdest, Rsrc1, Src2}{Multiply (with overflow)}
\pinstX{mulou Rdest, Rsrc1, Src2}{Unsigned Multiply (with overflow)}
Put the product of the integers from register {\tt Rsrc1} and {\tt
Src2} into register {\tt Rdest}.

\inst{mult Rsrc1, Rsrc2}{Multiply}
\instX{multu Rsrc1, Rsrc2}{Unsigned Multiply}
Multiply the contents of the two registers.  Leave the low-order word
of the product in register {\tt lo} and the high-word in register {\tt
hi}.

\pinst{neg Rdest, Rsrc}{Negate Value (with overflow)}
\pinstX{negu Rdest, Rsrc}{Negate Value (without overflow)}
Put the negative of the integer from register {\tt Rsrc} into
register {\tt Rdest}.

\inst{nor Rdest, Rsrc1, Src2}{NOR}
Put the logical NOR of the integers from register {\tt Rsrc1} and
{\tt Src2} into register {\tt Rdest}.

\pinst{not Rdest, Rsrc}{NOT}
Put the bitwise logical negation of the integer from register {\tt
Rsrc} into register {\tt Rdest}.

\inst{or Rdest, Rsrc1, Src2}{OR}
\instX{ori Rdest, Rsrc1, Imm}{OR Immediate}
Put the logical OR of the integers from register {\tt Rsrc1} and {\tt
Src2} (or {\tt Imm}) into register {\tt Rdest}.

\pinst{rem Rdest, Rsrc1, Src2}{Remainder}
\pinstX{remu Rdest, Rsrc1, Src2}{Unsigned Remainder}
Put the remainder from dividing the integer in register {\tt Rsrc1} by
the integer in {\tt Src2} into register {\tt Rdest}.  Note that if an
operand is negative, the remainder is unspecified by the MIPS
architecture and depends on the conventions of the machine on which
SPIM is run.

\pinst{rol Rdest, Rsrc1, Src2}{Rotate Left}