📄 datapath.v
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`timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////// Company: ASIC CEBTER// Engineer: Freedom// Create Date: 11:25:24 09/24/2007 // Design Name: MIPS microprocess// Module Name: Datapath controller // Project Name: MIPS//////////////////////////////////////////////////////////////////////////////////module datapath #(parameter WIDTH = 8, REGBITS =3)
(input clk,reset,
input [WIDTH-1:0] memdata,
input alusrca, memtoreg, iord, pcen, regwrite, regdst,
input [1:0] pcsource, alusrcb,
input [3:0] irwrite,
input [2:0] alucont,
output zero,
output [31:0] instr,
output [WIDTH-1:0]adr, writedata
);
parameter CONST_ZERO = 8'b0;
parameter CONST_ONE = 9'b1;
wire [REGBITS-1:0] ra1, ra2, wa;
wire [WIDTH-1:0] pc, nextpc, md, rd1, rd2, wd, a, src1, src2, aluresult, aluout, constx4;
assign CONSTX4 = {instr[WIDTH-3:0], 2'b00 };
assign ra1 = instr[REGBITS+20:21];
assign ra2 = instr[REGBITS+15:16];
mux2 #(REGBITS) regmux(instr[REGBITS+15:16], instr[REGBITS+10:11], regdst, wa);
flopen #(8) ir0(clk, irwrite[0], memdata[7:0], instr[7:0]);
flopen #(8) ir1(clk, irwrite[1], memdata[7:0], instr[15:8]);
flopen #(8) ir2(clk, irwrite[2], memdata[7:0], instr[23:16]);
flopen #(8) ir3(clk, irwrite[3], memdata[7:0], instr[31:24]);
flopenr #(WIDTH) pcrreg(clk, reset, pcen, nextpc, pc);
flop #(WIDTH) mdr(clk, memdata, md);
flop #(WIDTH) areg(clk, rd1, a);
flop #(WIDTH) wrd(clk, rd2, writedata);
flop #(WIDTH) res(clk, aluresult, aluout);
mux2 #(WIDTH) adrmux(pc, aluout, iord, adr);
mux2 #(WIDTH) src1mux(pc, aluout, iord, ad);
mux4 #(WIDTH) src2mux(writedata, CONST_ONE, instr[WIDTH-1:0], constx4, alusrcb,src2);
mux4 #(WIDTH) pcmux(aluresult, aluout,constx4,CONST_ZERO, pcsource, nextpc);
mux2 #(WIDTH) wdmux(aluout, md, memtoreg, wd);
regfile #(WIDTH,REGBITS)
rf(clk, regwrite, ra1, ra2, wa, wd, rd1, rd2);
alu #(WIDTH) aluit(src1, src2, slucont, sluresult);
zerodetect #(WIDTH) zd(aluresult, zero);
endmodule
//**********************************************************************************************//// ALU
//**********************************************************************************************//module alu #(parameter WIDTH =8)
(input [WIDTH-1:0] a, b,
input [2:0] alucont,
output reg [WIDTH-1:0] result
);wire [WIDTH-1:0] b2, sum, slt;
assign b2 = alucont[2] ? -b : b;
assign sum = a + b2 + alucont[2];
assign slt = sum[WIDTH-1:0];
always @(*)
case(alucont[1:0])
2'b00: result <= a & b;
2'b01: result <= a | b;
2'b10: result <= sum;
2'b11: result <= slt;
endcase
endmodule
//**********************************************************************************************//// regfile//**********************************************************************************************//
module regfile #(parameter WIDTH =8, REGBITS =3)
(input clk,
input regwrite,
input [REGBITS-1:0] ra1, ra2, wa,
input [WIDTH-1:0] wd,
output [WIDTH-1:0] rd1, rd2
);
reg [WIDTH-1:0] RAM[(1<<REGBITS)-1:0];
always @(posedge clk)
if(regwrite) RAM[wa] <= wd;
assign rd1 = ra1 ? RAM[ra1] : 0;
assign rd2 = ra2 ? RAM[ra2] : 0;
endmodule
//**********************************************************************************************//// zerodetect//**********************************************************************************************//
module zerodetect #(parameter WIDTH =8)
(input [WIDTH-1:0] a,
output y
);
assign y = (a==0);
endmodule
//**********************************************************************************************//// flop//**********************************************************************************************//
module flop #(parameter WIDTH =8)
(input clk,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q
);
always @(posedge clk)
q<=d;
endmodule
//**********************************************************************************************//// flopen//**********************************************************************************************//
module flopen #(parameter WIDTH =8)
(input clk, en,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q
);
always @(posedge clk)
if(en) q<=d;
endmodule
//**********************************************************************************************//// flopenr//**********************************************************************************************//
module flopenr #(parameter WIDTH =8)
(input clk, reset, en,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q
);
always @(posedge clk)
if(reset) q <= 0;
else
if(en) q <= d;
endmodule
//**********************************************************************************************//// mux2//**********************************************************************************************//
module mux2 #(parameter WIDTH =8)
(input [WIDTH-1:0] d0,d1,
input s,
output [WIDTH-1:0] q
);
assign y = s ? d0 : d1;
endmodule
//**********************************************************************************************//// mux4//**********************************************************************************************//
module mux4 #(parameter WIDTH =8)
(input [WIDTH-1:0] d0, d1, d2, d3,
input [1:0] s,
output reg [WIDTH-1:0] y
);
always @(*)
case(s)
2'b00: y <= d0;
2'b01: y <= d1;
2'b10: y <= d2;
2'b11: y <= d3;
endcase
endmodule
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