mips.v

来自「MIPS处理器的顶层VHDL代码」· Verilog 代码 · 共 40 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:        ASIC CEBTER
// Engineer:       Freedom
// Create Date:    21:05:24 09/20/2007 
// Design Name:    MIPS microprocess
// Module Name:    MIPS 
// Project Name:   MIPS
//////////////////////////////////////////////////////////////////////////////////

module MIPS #( parameter WIDTH = 8, REGBITS =3 )
             ( 
				   input             clk,reset,
				   input [WIDTH-1:0] memdata,
					output            memread, memwrite,
               output[WIDTH-1:0]	adr, writedata				
				  );
    wire [31:0] instr;
	 wire        zero, alusrca, memtoreg, irod, pcen, regwrite, regdst;
	 wire [1:0]  aluop, pcsource, alusrcb;
	 wire [3:0]  irwrite;
	 wire [2:0]  alucont;
	 
	 controller cont(
						  clk, reset, instr[31:26], zero, mwmreadm, memwrite,
						  alusrca, memtoreg, iord, pcen, regwrite, regdst,
						  pcsource, alusrcb, aluop, irwrite
						  );
    alucontrol ac (
	                aluop, instr[5:0], alucont
						 );
    datapath   #(WIDTH, REGBITS)
	            dp (
					    clk,reset, memdata, alusrca, memtoreg, iord, pcen,
						 regwrite, regdst, pcsource, alusrcb, irwrite, alucont,
						 zero, instr, adr, writedata
						 );

endmodule