mips_top.vhd

MIPS处理器VHDL代码

----------------------------------------------------------------------------------
-- Company:        ASIC Center
-- Engineer:       Freedom
-- Create Date:    13:43:46 09/18/2007 
-- Design Name: 
-- Module Name:    MIPS TOP module
-- Project Name:   MIPS
-- Description:    including mips microprocess and PADs
-- Revision:       MIPS_V01

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MIPS_top is
   generic(width  :   integer := 8;
           regbits:   integer := 3);
   port(
	      clk,reset        :    in  STD_LOGIC;
         memdata          :    in  STD_LOGIC_VECTOR(width-1 downto 0);
         memread,memwrite :    out STD_LOGIC;
	      adr,writedata    :    out STD_LOGIC_VECTOR(width-1 downto 0));

end MIPS_top;


			  
architecture main of MIPS_top is

--signal for MIPS_TOP connection
         signal pad_clk      :    STD_LOGIC;
			signal pad_reset    :    STD_LOGIC;
			signal pad_memdata  :    STD_LOGIC_VECTOR(width-1 downto 0);
			signal pad_memread  :    STD_LOGIC;
			signal pad_memwrite :    STD_LOGIC;
			signal pad_adr      :    STD_LOGIC_VECTOR(width-1 downto 0);
			signal pad_writedata:    STD_LOGIC_VECTOR(width-1 downto 0);
			
--signal for MIPS connection
         signal MIPS_clk      :    STD_LOGIC;
			signal MIPS_reset    :    STD_LOGIC;
			signal MIPS_memdata  :    STD_LOGIC_VECTOR(width-1 downto 0);
			signal MIPS_memread  :    STD_LOGIC;
			signal MIPS_memwrite :    STD_LOGIC;
			signal MIPS_adr      :    STD_LOGIC_VECTOR(width-1 downto 0);
			signal MIPS_writedata:    STD_LOGIC_VECTOR(width-1 downto 0);
			
         Signal st_0 : std_logic;
         Signal st_1 : std_logic;
			
-- PAD for normal I/O
  component PLBI8N 
    port (
           D     : out std_logic;
	        P     : inout std_logic;
	        A     : in std_logic;
	        CONOF : in std_logic;
	        NEN   : in std_logic;
	        PD    : in std_logic;
	        PEN   : in std_logic;
	        PU    : in std_logic;
	        SONOF : in std_logic
        );
  end component;
  
  component MIPS 
    port(
	      clk,reset        :  in  STD_LOGIC;
         memdata           :  in  STD_LOGIC_VECTOR(width-1 downto 0);
         memread,memwrite  :  out STD_LOGIC;
	      adr,writedata     :  out STD_LOGIC_VECTOR(width-1 downto 0));
  
  end component;



begin
   
	  inst_MIPS: MIPS
	  port map(
	           clk       =>   MIPS_clk,
				  reset     =>   MIPS_reset,
				  memdata   =>   MIPS_memdata,
				  memread   =>   MIPS_memread,
				  memwrite  =>   MIPS_memwrite,
				  adr       =>   MIPS_adr,
				  writedata =>   MIPS_writedata				  
				  );
	  
-- Constant '1' and '0' define
    st_0 <= '0';
    st_1 <= '1'; 

-- Input Port: clk
   i_PAD_CLK: PLBI8N
   port map(
      	    D      => MIPS_clk,
	          P      => pad_clk,
	          A      => st_0,
	          CONOF  => st_1,
	          NEN    => st_0,
	          PD     => st_0,
	          PEN    => st_0,
	          PU     => st_1,
	          SONOF  => st_0
             );
   pad_clk<=clk;
-- Input Port: reset
   i_PAD_reset: PLBI8N
   port map(
      	    D      => MIPS_reset,
	          P      => pad_reset,
	          A      => st_0,
	          CONOF  => st_1,
	          NEN    => st_0,
	          PD     => st_0,
	          PEN    => st_0,
	          PU     => st_1,
	          SONOF  => st_0
             );
    pad_reset<=reset;
-- Input Port: memdata(7)
   i_PAD_memdata_7: PLBI8N
   port map(
      	    D      => MIPS_memdata(7),
	          P      => pad_memdata(7),
	          A      => st_0,
	          CONOF  => st_1,
	          NEN    => st_0,
	          PD     => st_0,
	          PEN    => st_0,
	          PU     => st_1,
	          SONOF  => st_0
             );
    pad_memdata(7)<=memdata(7);
-- Input Port: memdata(6)
   i_PAD_memdata_6: PLBI8N
   port map(
      	    D      => MIPS_memdata(6),
	          P      => pad_memdata(6),
	          A      => st_0,
	          CONOF  => st_1,
	          NEN    => st_0,
	          PD     => st_0,
	          PEN    => st_0,
	          PU     => st_1,
	          SONOF  => st_0
             );
    pad_memdata(6)<=memdata(6);
-- Input Port: memdata(5)
   i_PAD_memdata_5: PLBI8N
   port map(
      	    D      => MIPS_memdata(5),
	          P      => pad_memdata(5),
	          A      => st_0,
	          CONOF  => st_1,
	          NEN    => st_0,
	          PD     => st_0,
	          PEN    => st_0,
	          PU     => st_1,
	          SONOF  => st_0
             );
    pad_memdata(5)<=memdata(5);
-- Input Port: memdata(4)
   i_PAD_memdata_4: PLBI8N
   port map(
      	    D      => MIPS_memdata(4),
	          P      => pad_memdata(4),
	          A      => st_0,
	          CONOF  => st_1,
	          NEN    => st_0,
	          PD     => st_0,
	          PEN    => st_0,
	          PU     => st_1,
	          SONOF  => st_0
             );
    pad_memdata(4)<=memdata(4);
-- Input Port: memdata(3)
   i_PAD_memdata_3: PLBI8N
   port map(
      	    D      => MIPS_memdata(3),
	          P      => pad_memdata(3),
	          A      => st_0,
	          CONOF  => st_1,
	          NEN    => st_0,
	          PD     => st_0,
	          PEN    => st_0,
	          PU     => st_1,
	          SONOF  => st_0
             );
    pad_memdata(3)<=memdata(3);
-- Input Port: memdata(2)
   i_PAD_memdata_2: PLBI8N
   port map(
      	    D      => MIPS_memdata(2),
	          P      => pad_memdata(2),
	          A      => st_0,
	          CONOF  => st_1,
	          NEN    => st_0,
	          PD     => st_0,
	          PEN    => st_0,
	          PU     => st_1,
	          SONOF  => st_0
             );
    pad_memdata(2)<=memdata(2);
-- Input Port: memdata(1)
   i_PAD_memdata_1: PLBI8N
   port map(
      	    D      => MIPS_memdata(1),
	          P      => pad_memdata(1),
	          A      => st_0,
	          CONOF  => st_1,
	          NEN    => st_0,
	          PD     => st_0,
	          PEN    => st_0,
	          PU     => st_1,
	          SONOF  => st_0
             );
    pad_memdata(1)<=memdata(1);	 
-- Input Port: memdata(0)
   i_PAD_memdata_0: PLBI8N
   port map(
      	    D      => MIPS_memdata(0),
	          P      => pad_memdata(0),
	          A      => st_0,
	          CONOF  => st_1,
	          NEN    => st_0,
	          PD     => st_0,
	          PEN    => st_0,
	          PU     => st_1,
	          SONOF  => st_0
             );
    pad_memdata(0)<=memdata(0);	 
-- Output Port: memread
   o_PAD_memread: PLBI8N
   port map(
      	    --D      => MIPS_memread,
	          P      => pad_memread,
	          A      => MIPS_memread,
	          CONOF  => st_0,
	          NEN    => st_1,
	          PD     => st_0,
	          PEN    => st_1,
	          PU     => st_1,
	          SONOF  => st_0
             );
    memread<=pad_memread;	 
-- Output Port: memwrite
   o_PAD_memwrite: PLBI8N
   port map(
      	    --D      => MIPS_memwrite,
	          P      => pad_memwrite,
	          A      => MIPS_memwrite,
	          CONOF  => st_0,
	          NEN    => st_1,
	          PD     => st_0,
	          PEN    => st_1,
	          PU     => st_1,
	          SONOF  => st_0
             );
    memwrite<=pad_memwrite;	 
-- Output Port: adr(7)
   o_PAD_adr_7: PLBI8N
   port map(
      	    --D      => MIPS_adr(7),
	          P      => pad_adr(7),
	          A      => MIPS_adr(7),
	          CONOF  => st_0,
	          NEN    => st_1,
	          PD     => st_0,
	          PEN    => st_1,
	          PU     => st_1,
	          SONOF  => st_0
             );
    adr(7)<=pad_adr(7);
-- Output Port: adr(6)
   o_PAD_adr_6: PLBI8N
   port map(
      	    --D      => MIPS_adr(6),
	          P      => pad_adr(6),
	          A      => MIPS_adr(6),
	          CONOF  => st_0,
	          NEN    => st_1,
	          PD     => st_0,
	          PEN    => st_1,
	          PU     => st_1,
	          SONOF  => st_0
             );
    adr(6)<=pad_adr(6);
-- Output Port: adr(5)
   o_PAD_adr_5: PLBI8N
   port map(
      	    --D      => MIPS_adr(5),
	          P      => pad_adr(5),
	          A      => MIPS_adr(5),
	          CONOF  => st_0,
	          NEN    => st_1,
	          PD     => st_0,
	          PEN    => st_1,
	          PU     => st_1,
	          SONOF  => st_0
             );
    adr(5)<=pad_adr(5);
-- Output Port: adr(4)
   o_PAD_adr_4: PLBI8N
   port map(
      	    --D      => MIPS_adr(4),
	          P      => pad_adr(4),
	          A      => MIPS_adr(4),
	          CONOF  => st_0,
	          NEN    => st_1,
	          PD     => st_0,
	          PEN    => st_1,
	          PU     => st_1,
	          SONOF  => st_0
             );
    adr(4)<=pad_adr(4);
-- Output Port: adr(3)
   o_PAD_adr_3: PLBI8N
   port map(
      	    --D      => MIPS_adr(3),
	          P      => pad_adr(3),
	          A      => MIPS_adr(3),
	          CONOF  => st_0,
	          NEN    => st_1,
	          PD     => st_0,
	          PEN    => st_1,
	          PU     => st_1,
	          SONOF  => st_0
             );
    adr(3)<=pad_adr(3);
-- Output Port: adr(2)
   o_PAD_adr_2: PLBI8N
   port map(
      	    --D      => MIPS_adr(2),
	          P      => pad_adr(2),
	          A      => MIPS_adr(2),
	          CONOF  => st_0,
	          NEN    => st_1,
	          PD     => st_0,
	          PEN    => st_1,
	          PU     => st_1,
	          SONOF  => st_0
             );
    adr(2)<=pad_adr(2);
-- Output Port: adr(1)
   o_PAD_adr_1: PLBI8N
   port map(
      	    --D      => MIPS_adr(1),
	          P      => pad_adr(1),
	          A      => MIPS_adr(1),
	          CONOF  => st_0,
	          NEN    => st_1,
	          PD     => st_0,
	          PEN    => st_1,
	          PU     => st_1,
	          SONOF  => st_0
             );
    adr(1)<=pad_adr(1);
-- Output Port: adr(0)
   o_PAD_adr_0: PLBI8N
   port map(
      	    --D      => MIPS_adr(0),
	          P      => pad_adr(0),
	          A      => MIPS_adr(0),
	          CONOF  => st_0,
	          NEN    => st_1,
	          PD     => st_0,
	          PEN    => st_1,
	          PU     => st_1,
	          SONOF  => st_0
             );
    adr(0)<=pad_adr(0);
	 
-- Output Port: writedata(7)
   o_PAD_writedata_7: PLBI8N
   port map(
      	    --D      => MIPS_writedata(7),
	          P      => pad_writedata(7),
	          A      => MIPS_writedata(7),
	          CONOF  => st_0,
	          NEN    => st_1,
	          PD     => st_0,
	          PEN    => st_1,
	          PU     => st_1,
	          SONOF  => st_0
             );
    writedata(7)<=pad_writedata(7);
-- Output Port: writedata(6)
   o_PAD_writedata_6: PLBI8N
   port map(
      	    --D      => MIPS_writedata(6),
	          P      => pad_writedata(6),
	          A      => MIPS_writedata(6),
	          CONOF  => st_0,
	          NEN    => st_1,
	          PD     => st_0,
	          PEN    => st_1,
	          PU     => st_1,
	          SONOF  => st_0
             );
    writedata(6)<=pad_writedata(6);
-- Output Port: writedata(5)
   o_PAD_writedata_5: PLBI8N
   port map(
      	    --D      => MIPS_writedata(5),
	          P      => pad_writedata(5),
	          A      => MIPS_writedata(5),
	          CONOF  => st_0,
	          NEN    => st_1,
	          PD     => st_0,
	          PEN    => st_1,
	          PU     => st_1,
	          SONOF  => st_0
             );
    writedata(5)<=pad_writedata(5);
-- Output Port: writedata(4)
   o_PAD_writedata_4: PLBI8N
   port map(
      	    --D      => MIPS_writedata(4),
	          P      => pad_writedata(4),
	          A      => MIPS_writedata(4),
	          CONOF  => st_0,
	          NEN    => st_1,
	          PD     => st_0,
	          PEN    => st_1,
	          PU     => st_1,
	          SONOF  => st_0
             );
    writedata(4)<=pad_writedata(4);
-- Output Port: writedata(3)
   o_PAD_writedata_3: PLBI8N
   port map(
      	    --D      => MIPS_writedata(3),
	          P      => pad_writedata(3),
	          A      => MIPS_writedata(3),
	          CONOF  => st_0,
	          NEN    => st_1,
	          PD     => st_0,
	          PEN    => st_1,
	          PU     => st_1,
	          SONOF  => st_0
             );
    writedata(3)<=pad_writedata(3);
-- Output Port: writedata(2)
   o_PAD_writedata_2: PLBI8N
   port map(
      	    --D      => MIPS_writedata(2),
	          P      => pad_writedata(2),
	          A      => MIPS_writedata(2),
	          CONOF  => st_0,
	          NEN    => st_1,
	          PD     => st_0,
	          PEN    => st_1,
	          PU     => st_1,
	          SONOF  => st_0
             );
    writedata(2)<=pad_writedata(2);
-- Output Port: writedata(1)
   o_PAD_writedata_1: PLBI8N
   port map(
      	    --D      => MIPS_writedata(1),
	          P      => pad_writedata(1),
	          A      => MIPS_writedata(1),
	          CONOF  => st_0,
	          NEN    => st_1,
	          PD     => st_0,
	          PEN    => st_1,
	          PU     => st_1,
	          SONOF  => st_0
             );
    writedata(1)<=pad_writedata(1);
-- Output Port: writedata0)
   o_PAD_writedata_0: PLBI8N
   port map(
      	    --D      => MIPS_writedata(0),
	          P      => pad_writedata(0),
	          A      => MIPS_writedata(0),
	          CONOF  => st_1,
	          NEN    => st_0,
	          PD     => st_0,
	          PEN    => st_0,
	          PU     => st_1,
	          SONOF  => st_0
             );
    writedata(0)<=pad_writedata(0);	 
end main;